User's Manual

MSD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
16
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Figure 1: Power On/Off Timing
Figure 2: Power On/Off Timing
Table 8: Timing Diagram Definitions
Timing
Description
Min
Unit
Tb
Time between VDD33 (3.3V )supplies valid, to WiFi reset (pin-
48;CHIP_PWD_L ) negation.
Note: have suitable 10K ohm Pull-up on pin-48, already. No extra
pull-up resistor is required.
5
µsec
Tc
Time between VDD33 (3.3V) supplies valid and
BT_RST_L (pin-32) negation
5
msec
Td
Time between WiFi reset (pin-48;CHIP_PWD_L ) negation and
VDD33 (3.3V) invalid, or time between BT_RST_L (pin-32) negation
and VDD33(3.3V) invalid.
0
µsec
Tf
Time of WiFi reset (pin-48; CHIP_PWD_L ) assertion during reset or
power down period. 3.3V should keep ON.
5
µsec
Tg
Time of BT_RST_L (pin-32) assertion during reset or power down
period. 3.3V should keep ON.
5
We suggest that Tb and Tf timing is greater than 5µsec but no longer than 100 msec.