User's Manual

MSD50NBT
Hardware Integration Guide
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WLAN FUNCTIONAL DESCRIPTION
Overview
The MSD50NBT WLAN block is based on the Qualcomm-Atheros AR6004 802.11a/b/g/n chipset. It is optimized
for low power embedded applications and is configured to operate in dual-band, two-stream (2x2 MIMO) mode.
Its functionality includes:
 Improved throughput on the link due to frame aggregation, RIFS (reduced inter-frame spacing), and half
guard intervals.
 Support for STBC (space time block codes) and LDPC (Low Density Parity Check) codes.
 Improved 11n performance due to features such as 11n frame aggregation (A-MPDU and A-MSDU) and
low-overhead host-assisted buffering (RX A-MSDU and RX A-MPDU). These techniques can improve
performance and efficiency of applications involving large bulk data transfers such as file transfers or high-
resolution video streaming.
Other functionality includes the following:
Feature
Description
Reset Control
CHIP_PWD_L and BT_RST_L pins must be asserted low to reset Wi-Fi and Bluetooth. After
these signals are de-asserted, the radio waits for host communication. Until then, all
modules except the host interface are held in reset.
Once the host has initiated communication, the radio turns on its crystal and then the PLL.
After all clocks are stable and running, the block resets are automatically de-asserted.
Note: Because BT chip derives clock from WLAN, the Bluetooth function should be
powered down/reset whenever WLAN is reset.
System Clocking
(RTC Block)
The MSD50NBT has an RTC block which controls the clocks and power going to other
internal modules. Its inputs consist of sleep requests from these modules and its outputs
consists of clock enable and power signals which are used to gate the clocks going to these
modules. The RTC block also manages resets going to other modules with the device. The
MSD50NBT’s clocking is grouped into two types: high-speed and low-speed.
High Speed Clocking
The reference 26 MHz clock source inside the MSD50NBT drives the PLL and RF synthesizer
of Wi-Fi and Bluetooth. To minimize power consumption, the reference clock source is
powered off in SLEEP, HOST_OFF, and OFF states.
Low Speed Clocking
The MSD50NBT has an 32.768 KHz oscillator that provide slow clock for BT to get deep
sleep mode.
Interface Clock
The host interface clock represents another clock domain for the MSD50NBT. This clock comes from
the SDIO and is independent from the other internal clocks. It drives the host interface logic as well
as certain registers which can be accessed by the host in HOST_OFF and SLEEP states.