User's Manual

M2US50NBT/M2SD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
11
Laird
Americas: [phone]
Europe: [phone]
Hong Kong: [phone] x026
Other functionality includes the following:
Feature
Description
System Clocking
(RTC Block)
An RTC block controls the clocks and power going to other internal modules. Its inputs
contain sleep requests from these modules and its outputs contain clock enable and
power signals which are used to gate the clocks going to these modules. The RTC block
also manages resets going to other modules with the device. The M2US50NBT/
M2SD50NBT’s clocking is grouped into two types: high-speed and low-speed.
High Speed Clocking
The reference 26 MHz clock source drives the PLL and RF synthesizer of Wi-Fi and
Bluetooth. To minimize power consumption, the reference clock source is powered off in
SLEEP, HOST_OFF, and OFF states.
Low Speed Clocking
These modules require an external sleep clock (32.768 KHz) source from host platform
through pin-50 on the NFGG golden finger. It is used to place BT into deep sleep mode. For
Wi-Fi only application, it is needed.
Interface Clock
The host interface clock represents another clock domain for the
M2US50NBT/M2SD50NBT. This clock comes from the SDIO and is independent from the
other internal clocks. It drives the host interface logic as well as certain registers which can
be accessed by the host in HOST_OFF and SLEEP states.
MAC/BB/RF Block
The M2US50NBT/M2SD50NBT Wireless MAC consists of five major blocks:
 Host interface unit (HIU) for bridging to the AHB for bulk data accesses and APB for
register accesses
 Ten queue control units (QCU) for transferring TX data
 Ten DCF control units (DCU) for managing channel access
 Protocol control unit (PCU) for interfacing to baseband
 DMA receive unit (DRU) for transferring RX data
Baseband Block
The M2US50NBT/M2SD50NBT baseband block (BB) is the physical layer controller for the
802.11b/g/n air interface.
 It modulates data packets in the transmit direction
 Detects and demodulates data packets in the receive direction.
 It has a direct control interface to the radio to enable hardware to adjust analog gains
and modes dynamically.
Clock Sharing
 Clock sharing is implemented on the M2US50NBT/M2SD50NBT. The Bluetooth chip
(CSR8811) receives a reference clock from the Wi-Fi chip (QCA6004). When Wi-Fi is in
power off/reset state, Bluetooth is also off.
 External 32.768 KHz signal present on pin 50 allows the BT chip to go into deep sleep
mode and consume lowest amount of power