User's Manual

BT900-Sx Hardware Integration Guide
Intelligent BTv4.0 Dual Mode Module
Americas: [phone] Option 2
Europe: [phone]
Hong Kong: [phone]
www.lairdtech.com/bluetooth
25 CONN-HIG-BT900
Note: The BT900 serial module output is at 3.3V CMOS logic levels (tracks VCC). Level
conversion must be added to interface with an RS-232 level compliant interface.
Some serial implementations link CTS and RTS to remove the need for handshaking. Laird does
not recommend linking CTS and RTS other than for testing and prototyping. If these pins are linked
and the host sends data at the point that the BT900 deasserts its RTS signal, then there is significant
risk that internal receive buffers will overflow, which could lead to an internal processor crash. This
will drop the connection and may require a power cycle to reset the module. Laird recommends
that the correct CTS/RTS handshaking protocol be adhered to for proper operation.
Table 14: UART Interface
Signal Name Pin
No
I/O Comments
SIO_1 / UART_TX 45 O SIO_1 (alternative function UART_TX) is an output, set high (in
FW).
SIO_0 / UART_RX 44 I SIO_0 (alternative function UART_RX) is an input, set with
internal pull-up (in FW).
SIO_2 / UART_RTS 46 O SIO_2 (alternative function UART_RTS) is an output, set low (in
FW).
SIO_3 / UART_CTS 35 I SIO_3 (alternative function UART_CTS) is an input, set with
internal pull-down (in FW).
The UART interface is also used to load customer developed smart BASIC application script.
5.6 SPI Bus
The SPI interface is an alternate function on SIO pins, configurable by smart BASIC.
The Module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CSB is
implemented using any spare SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a
3-wire (SPI_MOSI, SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from
multiple slaves. Individual chip select signals will be necessary for each of the slave devices
attached to a bus, but control of these is left to the application through use of SIO signals. I/O
data is double buffered.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.
Table 15: Peripheral supports
Signal Name Pin No I/O Comments
SPI_MOSI 8 O
This interface is an alternate function configurable by
smart BASIC. Default in the FW pin 8 and 10 are inputs.
SPIOPEN() in smart BASIC selects SPI function and
changes pin8and 10 to outputs (when in SPI master
mode).
SPI_MISO 7 I
SPI_CLK 10 O
5.7 I2C Interface
The I2C interface is an alternate function on SIO pins, configurable by smart BASIC command.
The Two-wire interface can interface a bi-directional wired-OR bus with two lines (SCL, SDA) and
has master /slave topology. The interface is capable of clock stretching. Data rates of 100 kbps
and 400 kbps are supported.