User's Manual

BT85x Series
Datasheet
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16
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I
2
S SCK and I
2
S WS become outputs in master mode and inputs in slave mode, while I
2
S SDO always stays as an
output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is
aligned with the MSB of the I
2
S bus, per the I
2
S specification. The MSB of each data word is transmitted one bit
clock cycle after the I
2
S WS transition, synchronous with the falling edge of bit clock. Left-channel data is
transmitted when I
2
S WS is low, and right-channel data is transmitted when I
2
S WS is high. Data bits sent by the
BT850 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising
edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider.
In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.
8.4.1. I
2
S Timing
Timing values specified in Table 15 are relative to high and low threshold levels.
Table 15: Timing for I2S transmitters and receivers
Transmitter Receiver Notes
Lower Limit Upper Limit Lower Limit Upper Limit
Min Max Min Max Min Max Min Max
Clock Period T T
tr
- - - T
r
- - -
Master Mode: Clock generated by transmitter or receiver
HIGH t
HC
0.35T
tr
- - - 0.35T
tr
- - -
LOW t
LC
0.35T
tr
- - - 0.35T
tr
- - -
Master Mode: Clock generated by transmitter or receiver
HIGH t
HC
- 0.35T
tr
- - - 0.35T
tr
- -
LOW t
LC
- 0.35T
tr
- - - 0.35T
tr
- -
Rise time t
RC
- - 0.15T
tr
- - - - -
Transmitter
Delay t
dtr
- - - 0.8T - - - -
Hold time t
htr
0 - - - - - - -
Receiver
Setup time t
sr
- - - - - 0.2T
r
- -
Hold time t
hr
- - - - - 0 - -