User's Manual

BT860
Datasheet
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14
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Figure 5 through Table 13 shows PCM Timing Diagram and Specifications for the master mode of long-frame.
Figure 5: PCM timing diagram (Long-Frame Sync, Master Mode)
Table 13: PCM Interface timing specifications (Long-Frame Sync, Master Mode)
Reference Characteristics Min. Typ. Max. Unit
1
PCM bit clock frequency
- - 12 MHz
2
PCM bit clock LOW
41 - - ns
3
PCM bit clock HIGH
41 - - ns
4
PCM_SYNC delay
0 - 25 ns
5 PCM_OUT delay 0 - 25 ns
6 PCM_IN setup 8 - - ns
7 PCM_IN hold 8 - - ns
8
Delay from rising edge of PCM_BCLK during last
bit period to PCM_OUT becoming high
impedance
0 - 25 ns