User's Manual

BT860
Datasheet
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Table 10: UART timing specifications
Reference Characteristics Min. Typ. Max. Unit
1
Delay time
UART_CTS_N low to UART TXD valid
- - 1.50
Bit
periods
2
Setup time
UART_CTS_N high before midpoint of stop bit
- - 0.67
Bit
periods
3
Delay time
Midpoint of stop bit to UART_CTS_N high
- - 1.33
Bit
periods
Figure 2: UART timing
8.3. PCM Interface
The BT860 supports two independent PCM interfaces that share the pins with I2S interfaces. The PCM interface
on the BT860 can connect to linear PCM Codec devices in master or slave mode. In master mode, the BT860
generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another
master on the PCM interface and are inputs to the BT860.
The configuration of the PCM interface may be adjusted by the host using vendor-specific HCI commands.
8.3.1. Slot Mapping
The BT860 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface.
These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where
the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent
on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these
interface rate is 1, 2, 4, 8 and 16, respectively. Transmit and receive PCM data from an SCO channel is always
mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices
to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the
PCM clock during the last bit of the slot.