User's Manual
Table Of Contents
- Revision History
- Contents
- 1 Scope
- 2 Operational Description
- 3 Block Diagram and Descriptions
- 4 Specifications
- 5 Pin Definitions
- 6 DC Electrical Characteristic
- 7 RF Characteristics
- 8 Interface
- 9 Power Supply and Regulation
- 10 Antenna Performance
- 11 Mechanical Dimensions and Land Pattern
- 12 Implementation Note
- 13 Application Note for Surface Mount Modules
- 14 FCC and IC Regulatory
- 15 European Union Regulatory
- 16 Ordering Information
- 17 Bluetooth SIG Approvals
BT830 Hardware Integration Guide
Version 0.1 (PRELIMINARY)
Americas: +1-800-492-2320 Option 2
Europe: +44-1628-858-940
Hong Kong: +852-2923-0610
www.lairdtech.com/bluetooth
18
CONN-GUIDE-BT830
(PRELIMINARY)
Figure 10: PCM Master Timing Short Frame Sync
8.8 PCM Slave Timing
Symbol
Parameter
Min
Typ
Max
Unit
f
sclk
PCM clock frequency (Slave mode: input)
64
-
2048
kHz
f
sclk
PCM clock frequency (GCI mode)
128
-
4096
kHz
t
sclkl
PCM_CLK low time
200
-
-
ns
t
sclkh
PCM_CLK high time
200
-
-
ns
8.9 PCM Slave Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
t
hsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
t
susclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
ns
t
dpout
Delay time from PCM_SYNC or PCM_CLK, whichever is later,
to valid PCM_OUT data (long frame sync only)
-
-
15
ns
t
dsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
15
ns
t
dpoutz
Delay time from PCM_SYNC or PCM_CLK low, whichever is
later, to PCM_OUT data line high impedance
-
-
20
ns
t
supinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
ns
t
hpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
ns