User's Manual

BT830 Hardware Integration Guide
Version 0.1 (PRELIMINARY)
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17
CONN-GUIDE-BT830
(PRELIMINARY)
Symbol
Parameter
Min
Typ
Max
Unit
PCM_SYNC low (long
frame sync only)
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 11: PCM Master Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
t
dmclkhsyncl
Delay time from
PCM_CLK high to
PCM_SYNC low
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
t
dmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
t
dmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
t
supinclkl
Set-up time for PCM_IN valid to PCM_CLK low
20
-
-
ns
t
hpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
0
-
-
ns
Figure 9: PCM Master Timing Long Frame Sync