User's Manual

TiWi-uB1 Module
DATASHEET
The information in this document is subject to change without notice.
330-0132 Copyright © 2013 LS Research, LLC Page 14 of 22
DEBUG INTERFACE CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
Characteristic
Condition
Min
Typ
Max
Unit
fclk_ dbg Debug clock frequency (see Figure 5)
12
MHz
t1 Allowed high pulse on clock (see Figure 5)
35
ns
t2 Allowed low pulse on clock (see Figure 5)
35
ns
t 3 EXT_RESET_N low to first falling edge on debug clock (see
Figure 7)
167
ns
t4 Falling edge on clock to EXT_RESET_N high (see Figure 7)
83
ns
t6EXT_RESET_N high to first debug command (see Figure 7)
83
ns
t6 Debug data setup (see Figure 6)
2
ns
t7 Debug data hold (see Figure 6)
4
ns
t8 Clock-to-data delay (see Figure 6)
Load = 10 pF
ns
Table 13 Debug Interface Timing
Figure 4 Slave Timing