User's Manual

TiWi-BLECA TRANSCEIVER MODULE
USER MANUAL
The information in this document is subject to change without notice.
TiWi-BLECA Copyright © 2013 LS Research, LLC Page 20 of 32
SLOW (32 KHZ) CLOCK SOURCE REQUIREMENTS
The slow clock is always supplied from an external source. It is input on the SLOW_CLK pin, and can be a digital
signal in the range of VIO only. For slow clock frequency and accuracy refer to Table 14. The external slow clock
must be stable before the system exits from shut down mode.
Parameter [1]
Condition
Symbol
Min
Typ
Max
Unit
Input slow clock frequency
32768
Hz
Input slow clock accuracy
WLAN, BT
+/-250
ppm
Input transition time T
r
/T
f
– 10% to 90%
T
r
/T
f
100
ns
Frequency input duty cycle
30
50
70
%
Input voltage limits
Square wave,
DC coupled
VIH
0.65 x VDDS
VDDS
V
peak
VIL
0
0.35 x VDDS
Input impedance
1
MW
Input capacitance
5
pF
Rise and fall time
100
ns
Phase noise
1 kHz
-125
dBc/Hz
[1] Slow clock is a fail safe input
Table 14 Slow Clock Source Requirements