User's Manual

BL652
Datasheet
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41
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The Laird DVK-BL652 development board incorporates an on-board JTAG J-link programmer for this purpose.
There is also the following JTAG connector which allows on-board JTAG J-link programmer signals to be routed
off the development board. The only requirement is that you should use the following JTAG connector on the
host PCB.
The JTAG connector MPN is as follows:
Reference
Part
Description and MPN (Manufacturers Part Number)
JP1
FTSH-105
Header, 1.27mm, SMD, 10-way, FTSH-105-01-L-DV Samtech
Note: Reference on the BL652 development board schematic (Figure 8) shows the DVK-BL652-xx
development schematic wiring only for the JTAG connector and the BL652 module JTAG pins.
Figure 8: BL652 development board schematic
SIO_18
U5
CON_SM_39
GND
1
SIO_23/SPI_MOSI
3
SIO_17
30
SIO_15
29
SIO_13/nAutoRUN
28
SIO_22
4
GND
27
NFC2/SIO_10
14
NFC1/SIO_09
15
SIO_25/SPI_CLK
38
nRESET
7
VDD_nRF
26
SIO_16/SFLASH_CLK
10
SIO_24/SPI_MISO
2
GND
16
SWDIO
5
SWDCLK
6
SIO_20/SFLASH_MOSI
8
SIO_18
9
SIO_14/SFLASH_MISO
11
SIO_12/SFLASH_CS
12
SIO_11
13
SIO_08/UART_RX
17
SIO_07/UART_CTS
18
SIO_06/UART_TX
19
SIO_05/UART_RTS/AIN3
20
SIO_04/AIN2
21
SIO_03/AIN1
22
SIO_02/AIN0
23
SIO_01/XL2
24
SIO_00/XL1
25
SIO_19
31
SIO_31/AIN7
32
SIO_30/AIN6
33
SIO_29/AIN5
34
SIO_28/AIN4
35
SIO_27/I2C_SCL
36
SIO_26/I2C_SDA
37
GND
39
GND
SWDIO_BLE
VCC_BLE
SIO_18
SWDCLK_BLE
VCC_BLE
nRESET_BLE
C9
0.1uF,16V
GND
GND
SWDIO
VCC_IO
SWDCLK
JP1
NOPOP (PIN HEADER,1.27mm 2X5P)
1 2
3 4
5 6
7 8
9 10
PIN HEADER,2.54mm 1X3P
J3
1
1
2
2
3
3
PIN HEADER,2.54mm 1X3P
J4
1
1
2
2
3
3
SWDCLK_BLE
nRESET_BLE
SIO_18
SWDIO_BLE