User's Manual

Table Of Contents
BL652
Datasheet
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Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend
linking CTS and RTS other than for testing and prototyping. If these pins are linked and the host sends data at the
point that the BL652 deasserts its RTS signal, then there is significant risk that internal receive buffers will
overflow, which could lead to an internal processor crash. This will drop the connection and may require a power
cycle to reset the module. We recommend that the correct CTS/RTS handshaking protocol be adhered to for
proper operation.
Table 20: UART interface
Signal Name
Pin No
I/O
Comments
SIO_06 / UART_Tx
17
O
SIO_06 (alternative function UART_Tx) is an output, set high
(in firmware).
SIO_08 / UART_Rx
14
I
SIO_08 (alternative function UART_Rx) is an input, set with internal
pull-up (in firmware).
SIO_05 / UART_RTS
18
O
SIO_05 (alternative function UART_RTS) is an output, set low
(in firmware).
SIO_07 / UART_CTS
16
I
SIO_07 (alternative function UART_CTS) is an input, set with internal
pull-down (in firmware).
The UART interface is also used to load customer developed smartBASIC application script.
SPI Bus
The SPI interface is an alternate function on SIO pins, configurable by smartBASIC.
The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CS is implemented using
any spare SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a 3-wire (SPI_MOSI,
SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves. Individual chip select
signals are necessary for each of the slave devices attached to a bus, but control of these is left to the application
through use of SIO signals. I/O data is double-buffered.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.
Table 21: SPI interfaces
Signal Name
Pin No
I/O
Comments
SPI_MOSI
3
O
This interface is an alternate function configurable by
smartBASIC. Default in the FW pin 3 and 38 are SIO inputs. SPIOPEN() in
smartBASIC selects SPI function and changes pin 3 and 38 to outputs (when in SPI
master mode).
SPI_MISO
2
I
SPI_CLK
38
O
SPI_CS
4
I
SPI_CS is implemented using any spare SIO digital output pins to allow for
multi-dropping. On Laird devboard SIO_22 (pin4) used as SPI_CS.
I2C Interface
The I2C interface is an alternate function on SIO pins, configurable by smartBASIC command.
The two-wire interface can interface a bi-directional wired-OR bus with two lines (SCL, SDA) and has master
/slave topology. The interface is capable of clock stretching. Data rates of 100 kbps and 400 kbps are supported.