User's Manual

60-2230C
Datasheet
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10. SDIO T IMING R EQUIREMENTS
The 60-2230C SDIO host interface pins are powered from the VIO_SD voltage supply. The SDIO electrical
specifications are identical for the 1-bit SDIO and 4-bit SDIO modes.
10.1 SDR12, SDR25, SDR50 Mode (up to 100MHz) (1.8V)
Figure 2:SDIO protocol timing Diagram--- SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)
Table 16: SDIO timing requirements--- SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)
Note: Over full range of values specified in the Recommended Operating Conditions unless otherwise
specified.
Symbol Parameter Condition Min. Typ. Max. Unit
f PP Clock Frequency SDR12/25/50 25 - 100 MHz
T ISU Input setup time SDR12/25/50 3 -- - ns
T IH Input Hold time SDR12/25/50 0.8 - - ns
T CLK Clock Time SDR12/25/50 10 - 40 ns
T CR ,T CF
Raise time, Fall time
T CR ,T CF <2ns (max) at 100 MHz
C CARD =10pF
SDR12/25/50 - - 0.2*T CLK ns
T ODLY
Output delay time
C L ≦ 30pF
SDR12/25/50 - - 7.5 ns
T OH
Output hold time
C L =15pF
SDR12/25/50 1.5 - - ns