User's Manual

SU60-SIPT
Datasheet
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http://ews-support.lairdtech.com
www.lairdtech.com/wireless
36
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Pin
#
Name Type
Voltage
Ref.
Description
If Not
Used
39 PCIE_TX_P O AVDD18 PCIe Transmit Data-Positive N/C
40 PCIE_TX_N O AVDD18 PCIe Transmit Data-Negative N/C
41 GND - - Ground GND
42 PCIE_RX_N I AVDD18 PCIe Receive Data-Negative N/C
43 PCIE_RX_P I AVDD18 PCIe Receive Data-Positive N/C
44 GND - - Ground GND
45 USB_DN I/O 3V3 USB Differential Data-Negative N/C
46 USB_DP I/O 3V3 USB Differential Data-Positive N/C
47 GND - - Ground GND
48 3V3 Power -
3.3V module power supply
Note: A 10u MLCC is needed for this pin. Place the
capacitor close to this pin as possible.
Ref. parts: GRM188R60J106ME47D (MURATA)
or CC0805KKX7R6BB106 (YAGO)
-
49 3V3 Power -
3.3V module power supply
Note: A 10u MLCC is needed for this pin. Place the
capacitor close to this pin as possible.
Ref. parts: GRM188R60J106ME47D (MURATA)
or CC0805KKX7R6BB106 (YAGO)
-
50 GND - - Ground GND
51 PMU_EN I
Enable input for all Regulators inside the 60-SIPT
series when it is “H” state. The 60-SIPT will be off
when it is “L” state.
Note: DO NOT float this pin. Pull-up to 3.3V with
100K for normal operation.
100K,
PU
52 VIO_SD Power - 1.8V/3.3V Digital I/O SDIO Power Supply -
53 SDIO_DATA0 I/O, PU VIO_SD SDIO 4-bit Mode DATA line Bit[0] N/C
54 SDIO_DATA1 I/O, PU VIO_SD SDIO 4-bit Mode DATA line Bit[1] N/C
55 SDIO_DATA2 I/O, PU VIO_SD SDIO 4-bit Mode DATA line Bit[2] N/C
56 SDIO_DATA3 I/O, PU VIO_SD SDIO 4-bit Mode DATA line Bit[3] N/C
57 SDIO_CMD I/O, PU VIO_SD SDIO 4-bit Mode Command/Response N/C
58 SDIO_CLK I, PU VIO_SD SDIO 4-bit Mode Clock Input N/C
59 GND - - Ground GND
60 UART_TXD
O,
WPU
VIO UART Serial Data Output N/C
61 UART_RXD I, WPU VIO UART Serial Data Input
N/C
62 UART_CTSn I, PU VIO UART Clear to Send (Active low) N/C
63 UART_RTSn
O,
WPU
VIO UART Request to Send (Active low) N/C
64 GND - - Ground GND
65 JTAG_TCK I, PU VIO JTAG Test Clock (input) N/C
66 JTAG_TMS I, PU VIO JTAG Test Controller Select (input) N/C