User's Manual

SU60-SIPT
Datasheet
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Pin
#
Name Type
Voltage
Ref.
Description
If Not
Used
No external circuitry is required to set a
configuration bit to “1”.
17 CONFIG_HOST0 I, PU AVDD18
Host interface configuration setting.
Detail configuration table are shown in Table 32
To set a configuration bit to “0”, attach a 100kΩ
resistor from the pin to ground.
No external circuitry is required to set a
configuration bit to “1”.
-
18 GND - - Ground GND
19 PCM_CLK I/O VIO
PCM Clock Signal (Optimal)
Optimal clock used for some codecs.
Output if Master mode; Input if Slave mode.
N/C
20 PCM_DOUT O VIO PCM Data N/C
21 PCM_SYNC I/O VIO
PCM Sync Pulse Signal
Output if Master mode; Input if Slave mode.
N/C
22 PCM_DIN I VIO PCM Data N/C
23 GPIO0 I/O VIO General purpose I/O pin. N/C
24 GND - - Ground GND
25 PCIE_WAKEn I/O VIO PCIe wake signal (input/output) (active low) N/C
26 PCIE_CLKREQn I/O VIO PCIe clock request (input/output) (active low) GND
27 PCIE_PERSTn I, PD VIO
PCIe host indication to reset the device (input)
(active low)
N/C
28 PCIE_W_DISABLEn I, PU VIO
PCIe host indication to disable the WLAN function
of the device (input) (active low)
N/C
29
LTE_SOUT/
JTAG_TDO
O, PD
O, PD
VIO
Serial data to external LTE device/
JTAG Test Data Out (TDO)
N/C
30
LTE_SIN/
JTAG_TDI
I, PD
I, PD
VIO
Serial data from external LTE device/
JTAG Test Data Input (TDI)
N/C
31 VIO Power - 1.8V/2.5V/3.3V Digital I/O Power Supply -
32 1.8V_OUT Power -
1.8V output from 60-SIPT series.
Used to pull-up the PDn pin for POR.
Note:
Do NOT used as power source for other circuits.
N/C
33 GND - - Ground GND
34 32KHz I, PU VIO
Sleep Clock Input
An external sleep clock of 32.768KHz with
minimum +/-250ppm is required for power saving
mode
-
35 GND - - Ground GND
36 PCIE_RCLK_N I AVDD18 PCIe Differential Clock Input-Negative N/C
37 PCIE_RCLK_P I AVDD18 PCIe Differential Clock Input-Positive N/C
38 GND - - Ground GND