User's Manual

SU60-SIPT
Datasheet
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
25
© Copyright 2017 Laird. All Rights Reserved
Americas: [phone]
Europe: [phone]
Hong Kong: [phone]
10.1.4 DDR50 Mode (50MHz) (1.8V)
Figure 6: SDIO CMD timing diagram--- DDR50 modes (50 MHz) (1.8V)
Figure 7: SDIO DAT[3:0] timing Diagram--- DDR50 modes (50 MHz) (1.8V)
Note: In DDR50 mode, DAT[3:0] lines are samples on both edges pf the clock (not applicable for CMD line)
Table 23: SDIO timing requirements – DDR50 modes (50 MHz)
Symbol Parameter Condition Min. Typ. Max. Unit
Clock
T CLK
Clock time
50MHz (max) between rising edge
DDR50 20 -- -- ns
T CR , T CF
Rise time, fall time
T CR , T CF <4.00ns (max) at 50MHz.
C CARD =10pF
DDR50 -- -- 0.2*T CLK ns
Clock Duty -- DDR50 45 -- 55 %
CMD Input (referenced to clock rising edge)
T IS
Input setup time
C CARD ≦10pF (1 card)
DDR50 6 -- -- ns