Data Sheet

LC840PA
Datasheet
https://www.lairdconnect.com
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Table 17: UART interface
Signal Name
Pin No
I/O
Comments
SIO_06 / UART_Tx
35
O
SIO_06 (alternative function UART_Tx) is an output, set high
(in firmware).
SIO_08 / UART_Rx
29
I
SIO_08 (alternative function UART_Rx) is an input, set with internal
pull-up (in firmware).
SIO_05 / UART_RTS
39
O
SIO_05 (alternative function UART_RTS) is an output, set low
(in firmware). (Optional in ProFLEX)
SIO_07 / UART_CTS
37
I
SIO_07 (alternative function UART_CTS) is an input, set with internal
pull-down (in firmware). (Unused in ProFLEX)
SIO_21 / UART2_Tx
12
O
SIO_21 (alternative function UART_Tx) is an output, set high
(in firmware).
SIO_20 / UART2_Rx
13
I
SIO_21 (alternative function UART_Rx) is an input, set with internal
pull-up (in firmware).
In ProFLEX, UART is the Host Interface and UART2 is the Debug Interface.
The UART interface is also used to load customer developed smartBASIC application script.
5.7 USB interface
LC840PA has USB2.0 FS (Full Speed, 12 Mbps) hardware capability. The ProFLEX firmware does not use the USB
interface.
Table 18: USB interface
Signal Name
Pin No
I/O
Comments
D-
17
I/O
D+
15
I/O
VBUS
24
When using the LC840PA VBUS pin (which is mandatory when a USB interface is used),
you MUST connect a 4.7uF capacitor to ground.
Note: You MUST power the rest of LC840PA module circuitry through the VDD pin
(OPTION1) or VDD_HV pin (OPTION2).
5.8 SPI Bus
The SPI interface is an alternate function on SIO pins. The ProFLEX firmware does not use SPI Bus.
The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CS is implemented using any spare
SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a 3-wire (SPI_MOSI, SPI_MISO,
SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves. Individual chip select signals are necessary for
each of the slave devices attached to a bus, but control of these is left to the application through use of SIO signals. I/O data is
double buffered.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.
Table 19: SPI interfaces
Signal Name
Pin No
I/O
Comments
SIO_40/SPI_MOSI
32
O
This interface is an alternate function configurable by smartBASIC.
Default in the FW pin 56 and 53 are SIO inputs. SPIOPEN() in
smartBASIC selects SPI function and changes pin 56 and 53 to outputs
(when in SPI master mode).
SIO_04/AIN2/SPI_MISO
34
I
SIO_41/SPI_CLK
30
O