Data Sheet

LC840PA
Datasheet
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An antenna inductance of Lant = 0.72 uH provides tuning capacitors in the range of 300 pF on each pin. The total capacitance
on NFC1 and NFC2 must be matched. Cint and Cp are small usually (Cint is 4pF), so can be omitted from calculation.
Battery Protection Note: If the NFC coil antenna is exposed to a strong NFC field, the supply current may flow in the opposite
direction due to parasitic diodes and ESD structures.
If the battery does not tolerate a return current, a series diode must be placed between the battery and the LC840PA to protect
the battery.
5.6 UART Interface
Note: The LC840PA has two UARTs. The ProFLEX firmware designates these UARTs as HOST and DEBUG, see section
3.2.
The Universal Asynchronous Receiver/Transmitter (UART) offers fast, full-duplex, asynchronous serial communication with built-
in flow control support (UART_CTS, UART_RTS) in HW up to one Mbps baud. Parity checking and generation for the ninth data
bit are supported.
UART_TX, UART_RX, UART_RTS, and UART_CTS form a conventional asynchronous serial data port with handshaking. The
interface is designed to operate correctly when connected to other UART devices such as the 16550A. The signaling levels are
nominal 0 V and 3.3 V (tracks VDD) and are inverted with respect to the signaling on an RS232 cable.
Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and UART_CTS is an
input. Both are active low.
These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS are all 3.3 V
level logic (tracks VDD). For example, when RX and TX are idle, they sit at 3.3 V. Conversely for handshaking pins CTS, RTS at
0 V is treated as an assertion.
The module communicates with the customer application using the following signals:
▪ Port/TxD of the application sends data to the module’s UART_RX signal line
▪ Port/RxD of the application receives data from the module’s UART_TX signal line
Figure 6: UART signals
Note: The LC840PA serial module output is at 3.3V CMOS logic levels (tracks VDD). Level conversion must be added to
interface with an RS-232 level compliant interface.
Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend linking CTS and
RTS other than for testing and prototyping. If these pins are linked and the host sends data at the point that the LC840PA de-
asserts its RTS signal, there is significant risk that internal receive buffers will overflow which could lead to an internal processor
crash. This drops the connection and may require a power cycle to reset the module. We recommend that you adhere to the
correct CTS/RTS handshaking protocol for proper operation.
LC840PA