Application Guide

Sterling-LWB Module

APPLICATION GUIDE

The information in this document is subject to change without notice.

5 Sterling-LWB Reference Design Modules

The LSR Sterling-LWB Module is supplied as a SIP package. LSR also offers two additional

modular variants supplied on a carrier board. These modules function both as the reference

design for the Sterling-LWB Module and as an all-inclusive module which can be assembled onto

the end users host board. Depending on the user’s antenna and footprint needs, there is a

module variant to suite most application requirements.

LSR recommends that for simplicity of both the host PCB design, as well as the manufacturing

process, that either the Chip Antenna or U.FL RF Connector version of the modules be used in

your design.

This section describes the details of the host PCB requirements. In order to use the modular

certification for the LSR Sterling-LWB SIP Module and variants for your design, it is critical that

the reference designs are correctly followed.

To integrate LSR Sterling-LWB SIP Module into a design using a chip antenna, the full 4-layer

Chip Antenna PCB reference design is shown in Figure 1, and Bill of Materials Table 4. Visit

http://www.lsr.com. For the latest Schematics and CAD files.

To integrate LSR Sterling-LWB SIP Module into a design using external U.FL connector, the full 4-

layer U.FL (external antenna) PCB reference design is shown in Figure 4 and Bill of Materials

Table 6. http://www.lsr.com. For the latest Schematics and CAD files.

It is not required to replicate the entire design, but what is required is the circuitry and layout as

it pertains to the antenna configuration being used in your design as shown in Figure 1 and

Figure 4.

Each of the LSR Sterling-LWB modules use a high speed SDIO interface for communication

between the host and the module. SDIO is quite sensitive to local sources of electrical noise

that may exist as a result of improper PCB layout design thus the SDIO interface requires special

attention when routing lines on the host PCB. SDIO paths should receive the highest priority

when routing to proactively minimizing trace length to mitigate transmission line effects. All of

the requirements for proper SDIO implementation is beyond the scope of this document,

however some of the high level requirements and recommendations are:

• 50 ohm line impedance is required for all SDIO lines.

• Placing zero ohm resistor in-line on all SDIO lines to allow for line tuning (if

required) on the host board.

• Keep all SDIO trace delay times as equal as possible

For further information regarding the SDIO interface, see the most recent SDIO Physical Layer

Specification provided by the SD Card Association.