Data Sheet

Features
We believe our simulation models are the most accurate and the most complete on the market today. A
summary of model capabilities is listed below:
• Fully simulates the entire instruction set (excluding operations for multiprocessor support).
• Supports all port and other I/O pin operations.
• Supports sleep and deep sleep modes.
• Supports Watchdog Timer.
• Supports General Purpose Timers in all modes.
• Supports Universal Asynchronous Receiver/Transmitter (UART) with FIFO mode.
• Supports Synchronous Serial Interface (SSI) with following frame types: Freescale, MICROWIRE, or Texas
Instruments.
• Supports Inter-Integrated Circuit (I2C) in all modes on appropriate devices.
• Supports Analog Comparators in all configurations of signal sources.
• Supports Analog-to-digital 10-bit converter (ADC) with several input channels plus internal temperature
sensor.
• Supports internal code and data FLASH memory including Cortex-M3 memory region protection.
• Supports all interrupt modes.
• Internally generated processor clock for performance. Event timing accurate to one clock period.
• Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses,
stack integrity checking, etc.).
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the ARM® Cortex™-M3:
x Bitband alias regions are of type XN (Execute Never).
x Cache information is not used.
x Systick calibration value register (SYST_CALIB) is ignored.
x Data Barrier instructions (DMB,DSB) are treated as NOP.
x Register PLLCFG is not modelled.
x Clock Verification Timers and Internal brown-out detector not modelled.
x Registers DR2R,DR4R,DR8R,SLR are not modelled.
x Loopback feature of the I2C Module is not documented and therefore not modelled.
Proteus Design Suite Page 8 Labcenter Electronics Ltd.