Data Sheet

Features
We believe our simulation models are the most accurate and the most complete on the market today. A
summary of model capabilities is listed below:
Fully simulates the entire instruction set (excluding operations for multiprocessor support).
Fully simulates FPU instruction set.
Supports all port and other I/O pin operations.
Supports powerdown modes.
Supports Window Watchdog Timer and Independent Watchdog Timer.
Supports General Purpose Timers (TIM1, TIM2-TIM5, TIM9-TIM11) in all modes.
Supports Real-time Clock.
Supports I2C with multimaster capability and packet error checking.
Supports SPI with Texas Instruments frame type and hardware CRC calculation.
Supports USART with full duplex asynchronous communication
Supports 12-bit ADC with several input channels, all conversion modes and configurable resolution.
Supports internal code and data FLASH memory including Cortex-M4 memory region protection.
Supports Universal Serial Bus on-the-go full speed (USB-OTG_FS) in device mode.
Supports all interrupt modes.
Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses,
stack integrity checking, etc.).
Fully integrated in to the VSM source level debugging system.
Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the ARM® Cortex™-M4:
x Clock security system is not implemented.
x SPI doesn't support IrDA and I2S audio protocols
x I2C::TRISE is not implemented
x I2C doesn't support SMBus protocol
x Tamper detection and backup functionality are not implemented
x Flash programming algorithm is not implemented.
x USB OTG Host capabilities and HNP protocol are not implemented.
x RTC doesn't perform reference clock detection
x RTC doesn't support calibration (RTC_CALR register)
x SDIO is not implemented
x Pins VCAP_1 and VCAP_2 are not modeled
x USART doesn't support Smartcard, LIN, IrDA protocols
Proteus Design Suite Page 14 Labcenter Electronics Ltd.