Data Sheet

Features
We believe our simulation models are the most accurate and the most complete on the market today. A
summary of model capabilities is listed below:
• Fully simulates the entire instruction set.
• Supports all port and other I/O pin operations.
• Supports sleep and deep sleep modes.
• Supports Watchdog Timer.
• Supports General Purpose Timers in all modes.
• Supports Universal Asynchronous Receiver/Transmitter (UART) with FIFO mode.
• Supports Synchronous Serial Interface (SSI) with following frame types: Freescale, Microwire, or Texas
Instruments.
• Supports Inter-Integrated Circuit (I2C) in all modes on appropriate devices.
• Supports Analog Comparators in all configurations of signal sources.
• Supports Analog-to-digital 10-bit converter (ADC) with several input channels plus internal temperature
sensor.
• Supports all interrupt modes.
• Internally generated processor clock for performance. Event timing accurate to one clock period.
• Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses,
stack integrity checking, etc.).
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the ARM® Cortex™-M0:
x Bitband alias regions are of type XN (Execute Never). Fetches from these regions are invalid.
x Cache information is not used.
x SysTick Calibration value Register (SYST_CALIB) is ignored.
x Alignment of memory accesses is not analyzed.
x Data Barrier instructions (DMB, DSB) are treated as NOP.
x Power monitoring and Brown-Out Detection circuit are not implemented.
x Flash programming firmware is not supported.
x LPC111X specific: Hysteresis bit CONIO.HYST is not modeled.
Proteus Design Suite Page 11 Labcenter Electronics Ltd.