Data Sheet

PCB Layout
115
Default clearance settings in the DRC manager
The graphics and edge clearances are fine at the default values.
Note that the edge/slot clearance field defines the clearance for power planes
against the board edge.
In addition to these clearances there is a board global rule for Resist-Trace clearance. This rule
enforces a clearance between the solder mask and copper and is intended to prevent exposed
slivers of copper on the manufactured PCB.
If, during route placement, you find these DRC errors, the solution is to either move the trace or
edit the pad style and change the guard gap (solder mask expansion) for that pad style.
Since there are no new rules required for this board we can move on to the net classes tab of
the dialogue.