Owner manual

VSBC-32 Configuration
ID 21168, Rev. 04 Page 4 - 7© PEP Modular Computers GmbH
4.2.3 VMEbus Control/Status Register
Figure 4-3: CS7 + 0x5 Bitmap
Address: CS7 + 0x5
Format: Byte
Access: Read/write
Value after HW Reset: See table
PEP Default Address: 0x 0D 00 00 05
Table 4-7: Register Description
Name
Register
Value
HW Reset Value
SW Reset Value
(PEP)
Description
Slot 1 Other Slot 1 Other
P_IRQ5
bit 7
1 0 0 0 0 Mailbox interrupt pending.
EN_DPR
bit 6
100
Value stored in
EEPROM
Dual-port SRAM (incl. mailbox
interrupts) enabled for VMEbus
requester. Base address estab-
lished through bits BADR0..3.
EN_BERR2
bit 5
10010
Enables the VMEbus error timer
(all VMEbus cycles).
Timeout = 128µs.
FSD
bit 4
11010
VMEbus “slot 1” detection flag of
system controller..
BADR3..0
bits 3..0
00
Value stored in
EEPROM
VMEbus address location of dual-
ported SRAM. Equivalent to
VMEbus address lines A23..A20,
programmable from 0x 00..0x 0F
in 1MB windows. Enabled by
EN_DPR:.
(See also following table.)
BADR2BADR3 BADR1 BADR0
01234567
P_IRQ5 FSDEN_BERR2EN_DPR