Owner manual

VSBC-32 Functional Description
ID 21168, Rev. 04Page 2 - 20 © PEP Modular Computers GmbH
2.6.6 Watchdog Timer
A 512ms watchdog timer triggers the on-board reset generator at timeout. Once
enabled via the board control/status register, the watchdog timer cannot be reset by
software. It must be re-triggered via the corresponding bit in the board control/status
register periodically within the timeout period. ‘Watchdog timer running’ is a status that is
displayed by the yellow front panel LED.
For the location of the Watchdog LED please refer to the VSBC-32(E) Frontpanel figure
in the “Introduction” chapter of this manual.
2.6.7 Reset Sources
The VSBC-32(E) interacts with the following reset sources:
2.6.8 “Slot 1” Detection
During power-up the VSBC-32(E) detects whether it is being used as a system control-
ler (slot 1). This information can be read from the VMEbus control/status register and is
valid until the next power-down of the system.
For a complete map of the VMEbus control/status register please refer to the relating
section in the Configuration chapter of this manual.
Table 2-7: VSBC-32(E) Reset Sources
Reset Source Identification
Push Button No
SYSRES* VME No
Watchdog WDG bit on-board (Board Control/Status Register)
Power Monitor (4.65V) Inside the MC68(EN)360