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VSBC-32

Combined VMEbus System Controller and

Serial Communications Controller Board

Manual ID 21168, Rev. Index 04

Jul 00

The product described in this manual is

in compliance with all applied CE stan-

dards.

Summary of content (110 pages)

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VSBC-32 Combined VMEbus System Controller and Serial Communications Controller Board Manual ID 21168, Rev. Index 04 Jul 00 The product described in this manual is in compliance with all applied CE standards.
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General VSBC-32 Revision History Manual/Product Title: VSBC-32 Manual ID Number: 21168 Rev. Index Brief Description of Changes 0100 Initial Issue 00/1 Aug 95 0200 General corrections 00/2 Dec 95 0201 J9 default setting changed 00/2 Nov 96 0300 General corrections and new manual structure 01 Dec 96 0301 New Preface 01 Aug 98 0311 Improvement to Fig. 2.1.3. In Appendices, corrections to flash addresses on pages MEM-2 to MEM-4, page MEM-5 replaced.
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VSBC-32 Contents Contents Preface Preface ..................................................................................................................... ix Proprietary Note ....................................................................................................... ix Trademarks .............................................................................................................. ix Explanation of Symbols ..........................................................................
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VSBC-32 1.5 Contents Applied Standards .................................................................................... 1 - 14 1.5.1 CE Compliance ................................................................................. 1 - 14 1.5.2 Mechanical Compliance ................................................................... 1 - 14 1.5.3 Environmental Tests ......................................................................... 1 - 14 1.6 Related Publications ..........................
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VSBC-32 Contents 2.6.6 Watchdog Timer ............................................................................... 2 - 20 2.6.7 Reset Sources ................................................................................. 2 - 20 2.6.8 “Slot 1” Detection ............................................................................. 2 - 20 2.7 Frontpanel Functions ............................................................................... 2 - 21 2.8 RTC and SRAM Data Retention .............
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VSBC-32 Appx. Contents A A. Memory Piggybacks ................................................................................... A - 3 A.1 General ..................................................................................................... A - 3 A.2 DM600 ...................................................................................................... A - 4 A.2.1 Board Layout and Jumper Location ................................................... A - 4 A.2.
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VSBC-32 Appx. Contents B B. Serial Interface Piggybacks ........................................................................ B - 3 B.1 General ...................................................................................................... B - 3 B.2 SI-10B2 ..................................................................................................... B - 4 B.2.1 Specifications ..................................................................................... B - 4 B.2.
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VSBC-32 Appx. Contents D D. OS-9 Cabling ............................................................................................. D - 3 D.1 OS-9 System – Terminal ........................................................................... D - 3 D.1.1 Software (XON/XOFF) or No Handshake .......................................... D - 3 D.1.2 Hardware Handshake (Set Terminal to CTS/DTR Handshake) ........ D - 4 D.2 OS-9 System – PC .............................................................
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VSBC-32 Preface Preface ID 21168, Rev.
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VSBC-32 Preface Preface Proprietary Note This document contains information proprietary to PEP Modular Computers. It may not be copied or transmitted by any means, disclosed to others or stored in any retrieval system or media, without the prior written consent of PEP Modular Computers GmbH or one of its authorized agents. The information contained in this document is, to the best of our knowledge, entirely correct.
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VSBC-32 Preface Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Please refer also to the section “Applied Standards” in this manual. Caution, Electric Shock! This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them.
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VSBC-32 Preface For Your Safety Your new PEP product was developed and tested carefully to provide all features necessary to ensure the renown electrical safety requirements. It was also designed for a long fault-free life. However, the life expectancy of your product can be drastically reduced by improper treatment during unpacking and installation.
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VSBC-32 Preface General Instructions on Usage • In order to maintain PEP’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by PEP Modular Computers and described in this manual or received from PEP Technical Support as a special handling instruction, will void your warranty.
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VSBC-32 Preface Two Year Warranty PEP Modular Computers grants the original purchaser of PEP products a TWO YEAR LIMITED as described in the following. However, no other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of PEP Modular Computers.
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VSBC-32 Introduction Chapter 1 Introduction ID 21168, Rev.
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VSBC-32 Introduction 1. Introduction 1.1 System Overview The PEP Modular Computers product described in this chapter operates with the VMEbus architecture. In addition, some products also support the CXC and/or Enhanced CXC (eCXC) local mezzanine interface standards which represent a streamlined variant of the VMEbus standard itself. Thus a wide range of I/O functions for industrial applications are supplied.
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VSBC-32 Introduction 1.2 Board Overview 1.2.1 Board-Specific Information The VSBC-32(E) is a 3U (Enhanced) CXC combined system and communications controller board that can operate in either a VMEbus or a mixed VMEbus+CXC environment. The board is based on the Motorola Quad Integrated Communications Controller “QUICC” MC68(EN)360. Therefore, it is particularly suitable for system control functions within applications with communications requirements.
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VSBC-32 Introduction The MC68EN360 processor is also available with two different clock rates: • • 25MHz 33MHz (this variant is again supplied with either 256kB or 1MB SRAM). The below described frontend connectivity and interface expandibility are common to all board variants. 1.2.
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VSBC-32 Introduction Maximum one CXM-SIO3 module can be controlled by a VSBC-32(E) board. The CXMSIO3 module provides access to internal communication signals of the base board that are transferred to the module via the CXC bus.
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VSBC-32 Introduction Loader can be re-entered, the memory contents analyzed and a further programming cycle initiated. Warning! To avoid damaging of your Bootstrap Loader and, consequently, leaving your board unusable, please read the separate Bootstrap Loader manual before re-setting the flash contents of your VSBC32 board. Operating Systems The VSBC-32(E) can operate under the following operating systems: • • OS-9 VxWorks® Drivers are available for both operating systems.
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VSBC-32 Introduction 1.3 Board Diagrams 1.3.1 System-Level Functional Block Diagram Figure 1-1: VSBC-32(E) System-Level Functional Block Diagram VSBC-32 Mainboard (Master) CXM-SIO3 * Legend: RS__[I]: 10Base_: RS232 non-optoisolated or RS485 optoisolated 10Base2 or 10Base5 or 10BaseT Ethernet * Serial I/O or Ethernet (Ethernet with VSBC-32E only) Page 1 - 8 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 1.3.2 Introduction Frontpanels Figure 1-2: VSBC-32(E) Frontpanel LED’s: • Green (“U”): • Yellow (“W”): • Red (“H”): General purpose Watchdog Halt U W H Pushbuttons: • RST (left): • AB (right): RST AB Reset Abort SI Piggyback Frontend Connector(s): The additio nal frontend conne cto r(s) depend(s) on the type of serial interface piggyback installed in combination with the VS BC -32(E) m ainboa rd. F or a ny details, please refer to the “Serial Interface Piggybacks” appendix in this manual.
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VSBC-32 1.3.3 Introduction Board Layouts Figure 1-3: VSBC-32(E) Board Diagram (front)] J12 J11 7 1 ST2A 3 1 2 J6 17 J14 32 FLASH/EPROM (Upper Data) 1 17 CPU / Serial Communications Controller 16 32 FLASH/EPROM (Lower Data) 1 7 1 ST2B ST2C 3 1 2 J13 SI Piggyback 7 1 16 BDM 12 6 BU3 1 BU4 2 1 2 49 50 EEPROM SRAM 49 50 Memory Piggyback J10 J9 FLASH/EPROM: Upper Data: Lower Data: D8-D15, even Byte addresses D0-D7, odd Byte addresses BDM: Background Debug Mode.
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VSBC-32 Introduction Figure 1-4: VSBC-32(E) Board Diagram (reverse)] J7 3 1 2 3 1 2 J8 J11 3 1 2 J7 3 1 2 J11 3 1 2 3 1 2 J8 JUMPERS MAGNIFIED Warning! Solder jumpers are factory-set. To avoid possible damage to your equiment, please do not alter them. ID 21168, Rev.
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VSBC-32 Introduction 1.4 Technical Specifications Table 1-2: VSBC-32(E) Technical Specification (Sheet 1 of 3) VSBC-32(E) Specification Board Variants • • VSBC-32: VSBC-32E: MC68360 processor, MC68EN360 processor Combined CPU/Serial Communications Controller • • MC68360: MC68EN360: 25 MHz, no Ethernet capability 25MHz or 33 MHz, Ethernet capability CPU performance: Serial I/O perform.
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VSBC-32 Introduction Table 1-2: VSBC-32(E) Technical Specification (Sheet 2 of 3) VSBC-32(E) Specification Communication Standards • • Serial I/O (RS232, RS422, RS485) Ethernet (VSBC-32E only) Mainboard Connectivity • Non-optoisolated RS232 serial interface (two RJ12 connectors, on frontpanel) One set of piggyback interface connectors for serial interface (SI) piggybacks (two 13-pin row fe/male connectors) One set of memory piggyback interface connectors (two 50-pin row fe/male connectors) Backgrou
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VSBC-32 Introduction Table 1-2: VSBC-32(E) Technical Specification (Sheet 3 of 3) VSBC-32(E) Specification Power Consumption • • VSBC-32: VSBC-32E: Temperature Ranges Operation: 0° C to 70°C -40° C to +85° C typ. 3.0W typ. 3.5W (standard) (extended) Storage: -55° C to +125°C Humidity 0..95%, non-condensing Dimensions 4HP/3U Eurocard (100mm x 160mm) Weight Mainboard: Serial interface piggyback: Memory piggyback: 130g 20..30g 30g 1.5 Applied Standards 1.5.
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VSBC-32 Introduction 1.6 Related Publications 1.6.1 • • • • • • ANSI/VITA: VME64 Draft Specification 1-1994, Rev. 1.9 VITA: CXC Specification, Rev. 2.0 PEP Modular Computers CXC MPI Draft Specification, Rev. 3.1 (ID 12190) PEP Modular Computers CXC Reference Manual, ID 05263 PEP Modular Computers CXM-SIO3 Manual (ID 14411) PEP Modular Computers CXM-SCCI Manual (ID 03545) 1.6.
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VSBC-32 Functional Description Chapter 2 Functional Description ID 21168, Rev.
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VSBC-32 Functional Description 2. Functional Description 2.1 General Information The VSBC-32(E) is a 3U VMEbus combined system and communications controller board based on the Motorola Quad Integrated Communications Controller “QUICC” MC68(EN)360. Depending on the controller chip used and the SRAM size, there are four board variants with different characteristics. The following table provides an overview of the various VSBC-32(E) board variants.
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VSBC-32 Functional Description 2.2 Specifics 2.2.1 System Control Functionality Under the aspect of system control the on-chip 32-bit CPU core of the Motorola MC68(EN)360 provides system integration at different processor frequencies. The processor core acts essentially as a Motorola CPU32 microprocessor operating at 25MHz or 33MHz without cache memory. In addition, the MC68(EN)360 offers background debugging via the on-chip “Background Debug Mode” which allows direct communication with the CPU.
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VSBC-32 Functional Description Table 2-2: External Autovector and Mailbox Interrupts Source Interrupt Source Interrupt Type ABORT / ACFAIL MC68(EN)360, pin IRQ7 Autovector 7 Reserved MC68(EN)360, pin IRQ6 Autovector 6 Mailbox IRQ MC68(EN)360, pin IRQ5 Autovector 5 Reserved MC68(EN)360, pin IRQ4 Autovector 4 SYSFAIL MC68(EN)360, pin IRQ3 Autovector 3 Reserved MC68(EN)360, pin IRQ2 Autovector 2 Reserved MC68(EN)360, pin IRQ1 Autovector 1 Mailbox Pending Bit P_IRQ5 Control/status re
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VSBC-32 Functional Description A schematic overview of all possible memory configurations is given in the figure on the next page. Figure 2-1: VSBC-32 Memory Configuration Variants Mainboard VSBC-32 MC68360 SRAM 256kB 25MHz RTC VSBC-32E MC68EN360 25MHz 33MHz SRAM 256kB CPU/Serial Comm. Controller or SRAM 1MB 2kbit EEPROM SRAM DRAM + Flash Flash or EPROM CPU Options (256kB or 1 MB) Memory Piggybacks - 2.2.3 1MB 4MB 8MB 16MB 32MB 64MB DRAM + 0 DRAM + 1,2 DRAM + 1,2 DRAM + 1,2 DRAM + 0.
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VSBC-32 2.2.4 Functional Description Serial Communications Control Under the aspect of serial communications control, a major advantage of the MC68(EN)360 serial communications controller core SIM60 is its compatibility with all important communication standards. A detailled description of all control functions is provided on the following pages alongside with a comprehensive list of the possible serial interface piggybacks and their connectors.
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VSBC-32 Functional Description serial interface (SI) piggybacks (RS232, RS485, Ethernet). The SCC1 channel of the MC68(EN)360 provides the interface to the serial interface (SI) piggyback installed on the VSBC-32(E). All other channels of the controller (SCC2, SCC3 and SCC4) are ported to the CXC interface except for the SI-PB232 piggyback which has on-board additional control provided by the SCC4 channel through the piggyback interface for serial interface piggybacks.
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VSBC-32 Functional Description Depending on whether the piggyback interface for serial interface (SI) piggybacks is configured as an Ethernet port (board versions with Ethernet piggyback) or not, the serial interfaces channels of the VSBC-32(E) can assume the functions described in the following figure.
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VSBC-32 Functional Description 2.
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VSBC-32 Functional Description 2.4 Board Interfaces The following section provides a description of the mainboard interface connector pinouts. For a detailled list and description of the connectors of the serial interface/communication piggybacks and of the frontpanel interface connectors please refer to the “SI Piggybacks” appendix of this manual as well as to the CXM-SIO3 user’s manual and its “Serial Communications Piggybacks” appendix respectively. 2.4.
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VSBC-32 2.4.2 Functional Description Piggyback Interface Connectors for Serial Interface Piggybacks The VSBC-32(E) is equipped with a set of piggyback interface connectors for serial interface (SI) piggybacks (three 7-pin row male connectors). The pinout of these piggyback interface connectors includes all signals for serial I/O (RS232), PROFIBUS (RS485) and Ethernet (10BaseT, 10Base5, 10Base2) communication. Note...
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VSBC-32 2.4.5 Functional Description Background Debug Mode Interface Connector The VSBC-32(E) is equipped with a background debug mode (BDM) interface connector (one 12-pin row male connector). This connector allows an external debugger to be interfaced to the MC68(EN)360 for controlling purposes. The interface connector is specified by Motorola. The pinouts of the BDM interface connector are shown in the following table. For any further details, please refer to the Motorola MC68(EN)360 User’s Manual.
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VSBC-32 Functional Description The VSBC-32(E) also provides a bus monitor for the VMEbus. A 128µs bus error timer monitors the cycle lengths of the VMEbus data transfer and generates a VMEbus BERR* signal on timeout. This timer is enabled and disabled via the VMEbus control/status register which contains alsao a timeout status bit in order to identify the bus errors generated by the bus monitor.
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VSBC-32 Functional Description For general CXC information, including generic pinouts and a comparison of the MC68(EN)360 and the MC68302 CPU pinouts on the CXC, please refer to the “CXC” appendix attached to this manual, the PEP Modular Computers CXC Reference Manual or to the CXC Specification. 2.5 VSBC-to-VSBC-32 System Upgrading In the following the porting information required by customers wanting to upgrade their VSBC-based systems to an VSBC-32 based one is supplied.
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VSBC-32 Functional Description Table 2-5: IUC/IUC-32 Porting Information (Sheet 1 of 2) CXC Function Pin MC68302 HW Comp.
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VSBC-32 Functional Description Table 2-5: IUC/IUC-32 Porting Information (Sheet 2 of 2) CXC Function Pin MC68302 MC68(EN) HW 360 Comp.
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VSBC-32 Functional Description 2.6 Special Board Functions 2.6.1 Real-Time Clock The three-wire serial interface real-time clock V3021 is a 1-bit device which is accessible over the CS6 of the MC68(EN)360. Its time-keeping features include as follows: • • • seconds, minutes, hours, day of month, month, year, week day and week number in BCD format; leap year and week number correction; stand-by supply smaller than 1µA.
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VSBC-32 2.6.5 Functional Description Bus Error Timers The VSBC-32(E) provides an on-board bus error timer and a VMEbus error timer.
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VSBC-32 2.6.6 Functional Description Watchdog Timer A 512ms watchdog timer triggers the on-board reset generator at timeout. Once enabled via the board control/status register, the watchdog timer cannot be reset by software. It must be re-triggered via the corresponding bit in the board control/status register periodically within the timeout period. ‘Watchdog timer running’ is a status that is displayed by the yellow front panel LED.
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VSBC-32 Functional Description 2.7 Frontpanel Functions The frontpanel status indicators consist of three LED’s with the following functions: • • • Yellow Green Red Watchdog LED General Purpose CPU Halt or Reset The green LED is user-defined by the customer. It is set by the software during startup when the MC68(EN)360 is initialized.
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VSBC-32 Functional Description Figure 2-7: Gold-Cap Charge and Dischage Characteristics Charge Characteristics of the Gold-Caps U(Volts) 4 3 2 1 0 0 0.1 1 5 10 60 120 Time (Minutes) Discharge Characteristics of the Gold-Caps U(Volts) 4 3 2 1 0 25 50 100 150 170 Time (Hours) Page 2 - 22 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 Functional Description 2.9 Address Decoder 2.9.1 Basic Structure The address decoder of the VSBC-32(E) consists of external logic and the MC68(EN)360 internal memory controller. The MC68(EN)360’s internal chip select logic decodes all the basic address areas following its initialization. The eight chip select outputs of the processor are connected to the different devices as shown in the following tablle.
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VSBC-32 Installation Chapter 3 Installation ID 21168, Rev.
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VSBC-32 Installation 3. Installation 3.1 Hardware Installation The board described in this manual can be installed in the system slot of any VMEbus compatible computer. The frontpanel of the board should be safely secured by screws to the chassis to avoid lossening of the board through vibration and to ensure correct earth connection. Caution, Electric Shocks! Switch off the VMEbus system before installing the board in a free VMEbus slot.
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VSBC-32 Installation To remove the board, please proceed as follows: • • • Ensure that the safety requirements indicated above are observed Disconnect any interfacing cables that may be connected to the board Disengage the board retaining mechanism by pressing down on the board release handle disengaging the board from the backplane connector and pull the board out of the slot. 3.1.
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VSBC-32 Configuration Chapter 4 Configuration ID 21168, Rev.
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VSBC-32 Configuration 4. Configuration 4.1 Hardware Configuration The VSBC-32(E) has fifteen jumpers fitted to the board. The list of default jumper settings is shown below. A board layout with all jumper locations and pinouts is supplied in the Board Layouts section of the Introduction chapter of this manual. 4.1.
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VSBC-32 4.1.2 Configuration Solder Jumpers The following parameters are selected via solder jumpers: • • • • • • CPU/bus clock frequency (J1/J2/J3) Communications clock frequency (J4) Serial EEPROM write protection (J5) Connection of protective and signal Ground (J6) CXC interface connector pin A5 function assignment (J11) SRAM size (J7/J8) Warning! All solder jumpers are factory set. Alteration of their settings can result in damage to the board.
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VSBC-32 Configuration 4.2 Software Configuration 4.2.1 Address Map Software applications may require to configure data in the VSBC-32(E) registers. For this purpose, the configurable memory is described in the following. The address map in the table below is based on the recommended default initialization of the MC68(EN)360 chip select logic.
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VSBC-32 4.2.2 Configuration Board Control/Status Register Address: CS7 + 0x7 Format: Byte Access: Read/write Value after HW Reset: 0 PEP Default Address: 0x 0D 00 00 07 Figure 4-2: CS7 + 0x7 Bitmap 7 WDG 6 5 4 BERR2 BERR1 EN_WDG 3 2 TR_WDG EN_BERR1 1 0 ACFAIL LED_G Table 4-6: Register Description Name Register Value Access Description Read/Write Set by watchdog timer when timout has been reached.
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VSBC-32 4.2.3 Configuration VMEbus Control/Status Register Address: CS7 + 0x5 Format: Byte Access: Read/write Value after HW Reset: See table PEP Default Address: 0x 0D 00 00 05 Figure 4-3: CS7 + 0x5 Bitmap 7 6 5 4 P_IRQ5 EN_DPR EN_BERR2 FSD 3 2 BADR3 BADR2 1 0 BADR1 BADR0 Table 4-7: Register Description Name P_IRQ5 bit 7 EN_DPR bit 6 EN_BERR2 bit 5 FSD bit 4 BADR3..0 bits 3..0 ID 21168, Rev.
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VSBC-32 Configuration Table 4-8: Board Base Addresses BADR3..0 Board Base Address BADR3..0 Board Base Address 0000 0x 00 00 00 1000 0x 80 00 00 0001 0x 10 00 00 1001 0x 90 00 00 0010 0x 20 00 00 1010 0x A0 00 00 0011 0x 30 00 00 1011 0x B0 00 00 0100 0x 40 00 00 1100 0x C0 00 00 0101 0x 50 00 00 1101 0x D0 00 00 0110 0x 60 00 00 1110 0x E0 00 00 0111 0x 70 00 00 1111 0x F0 00 00 4.2.
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VSBC-32 Memory Piggybacks Appendix A Memory Piggybacks ID 21168, Rev.
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VSBC-32 Memory Piggybacks A. Memory Piggybacks A.1 General The Memory Piggybacks described herein provide main memory capability for the storage of progam code and data either in DRAM or flash memory. Various configurations of DRAM and flash memory as indicated in the table below are available for a wide variety of PEP CPU boards. All configurations have 32-bit access and a maximum address range of 64 MB. In addition jumpers are available for providing write protection.
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VSBC-32 Memory Piggybacks A.2 DM600 The DM600 is a memory piggyback fitted with: • • DRAM: Flash Memory: 4 MB 1, 2, or 4 MB A.2.1Board Layout and Jumper Location Figure A-1: DM600 Memory Piggyback 4 J1 3 1 2 1 49 2 50 Legend: 1. Flash Memory 2. DRAM A.2.
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VSBC-32 Memory Piggybacks A.3 DM601 The DM601 is a memory piggyback fitted with: • • DRAM: Flash Memory: 16 MB 1, 2, or 4 MB A.3.1Board Layout and Jumper Location Figure A-2: DM601 Memory Piggyback 4 J1 3 1 2 1 49 2 50 Legend: 1. Flash Memory 2. DRAM A.3.
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VSBC-32 Memory Piggybacks A.4 DM602 The DM602 is a memory piggyback fitted with: • • DRAM: Flash Memory: 1 MB 0, 1, or 2 MB A.4.1Board Layout and Jumper Location Figure A-3: DM602 Memory Piggyback J1 J2 1 49 2 50 2 Legend: 1. Flash Memory 1 2. DRAM A.4.
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VSBC-32 Memory Piggybacks A.5 DM603 The DM603 is a memory piggyback fitted with: • • DRAM: 32 MB FLASH MEMORY:0, 0.5 (512 KB), 1, 2, or 4 MB A.5.1 Board Layout and Jumper Location Figure A-4: DM603 Memory Piggyback 1 49 2 50 Legend: J1 1. Flash Memory 2 1 J2 1 49 2 50 2. DRAM A.5.
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VSBC-32 Memory Piggybacks A.6 DM604 The DM604 is a memory piggyback fitted with: • • DRAM: 8 MB FLASH MEMORY:1or 4 MB A.6.1 Board Layout and Jumper Location Figure A-5: DM604 Memory Piggyback 1 49 2 50 J2 J1 Legend: 1. Flash Memory 1 2. DRAM 2 1 2 A.6.
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VSBC-32 Memory Piggybacks A.7 DM605 The DM605 is a memory piggyback fitted with: • • DRAM: 64 MB FLASH MEMORY:1or 4 MB A.7.1 Board Layout and Jumper Location Figure A-6: DM605 Memory Piggyback J2 1 49 2 50 J1 Legend: 1. Flash Memory 2 2. DRAM A.7.
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VSBC-32 Serial Interface Piggybacks Appendix B Serial Interface Piggybacks ID 21168, Rev.
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VSBC-32 Serial Interface Piggybacks B. Serial Interface Piggybacks B.1 General The serial interface (SI) piggybacks described herein adapt the multi-protocol serial channels of the 68EN360 controller chip to one of the following physical interfaces: • • • • • 10Base2 (thin or cheapernet) Ethernet, 10Base5 (AUI) Ethernet, 10BaseT (twisted pair) Ethernet, RS-232 modem compatible, RS485 optoisolated (PROFIBUS), and are available for a wide variety of PEP CPU boards.
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VSBC-32 Serial Interface Piggybacks B.2 SI-10B2 The SI-10B2 is a physical cheapernet (10Base2) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to a 50 ohm coax cable via an RG58 BNC ‘T’ connector. The SI6-10B2 has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data transmission. B.2.1 Specifications On-board termination: None (Cheapernet cable is terminated at both ends) Max.
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VSBC-32 Serial Interface Piggybacks B.3 SI-10B5 The SI-10B5 is a physical AUI interface to the 68EN360 Controller chip. B.3.1 Specifications On-board termination: None Max. Baudrate 10Mbit/s according toEthernet specification B.3.
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VSBC-32 Serial Interface Piggybacks B.4 SI-10BT The SI-10BT is a physical twisted pair (10BaseT) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to an unshielded 100ohm twisted-pair cable via an RJ45 telephone jack. The SI-10BT has two LEDs fitted: a red LED indicates collision detection and a yellow LED for data. B.4.1 Specifications On-board termination: 100ohm Max. Baudrate: 10Mbit/s according to Ethernet specification B.4.
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VSBC-32 4.2.1 Serial Interface Piggybacks SI-10BT Jumper Settings Table B-4: Jumper J1 – Squelch Threshold Setting Descirption Open Normal Set 4.5dB reduced threshold Default settings are in italics. Table B-5: Jumper J2 – Link Test Setting Descirption Open Link Test enabled Set Link Test disabled Default settings are in italics. Table B-6: Jumper J3 – Shielding Setting Descirption Open Unshielded, 100 ohm termination Set Shielded, 150ohm termination Default settings are in italics.
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VSBC-32 Serial Interface Piggybacks B.5 SI-PB232 The SI-PB232 provides two RS-232 serial interfaces to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards via two RJ45 telephone jacks. B.5.
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VSBC-32 Serial Interface Piggybacks B.6 SI-PB485-ISO The SI-PB485-ISO is an RS-485 optoisolated interface piggyback for 2-wire half-duplex (PROFIBUS) connection. It has one LED fitted indicating data transmission. B.6.1 Specifications On-board termination: 150ohm, jumper selectable Isolation voltage Optocoupler specified up to 2.5kV Max. baudrate 1.5MBaud B.6.
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VSBC-32 B.6.3 Serial Interface Piggybacks SI-PB485-ISO Jumper Settings Table B-9: Jumpers J1 and J2 – End-of-Line Termination Setting Description Open No internal line termination Set internal line termination Default settings are in italics. Table B-10: Jumpers J3 and J4 – Idle Setting Setting Description Open No internal idle status Set Internal idle status Default settings are in italics.
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VSBC-32 CXC Appendix C CXC ID 21168, Rev.
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VSBC-32 CXC C. CXC The Controller eXtension Connector (CXC) is the local interface. It contains a 16-bit data bus, seven address lines and eight decoded chip select lines. Each select line has 256 Bytes. In total, there are eight select signals. C.1 CXC Address Ranges The following tables provide address range information for both the CXC standard backplanes as well as the enhanced CXC backplanes (ECXC) for the CPU boards indicated.
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VSBC-32 CXC Table 1-2: Enhanced CXC Address Range Slot Chip Select VSBC-860 VSBC-32 IUC32 VM642 VM662 BU2 CS0 0xB0000000 0x10000000 0x10000000 BU3 CS1 0xB1000000 0x11000000 0x11000000 BU4 CS2 0xB2000000 0x12000000 0x12000000 BU5 CS3 0xB3000000 0x13000000 0x13000000 BU6 CS4 0xB4000000 0x14000000 0x14000000 BU7 CS5 0xB5000000 0x15000000 0x15000000 BU8 CS6 0xB6000000 0x16000000 0x16000000 BU0* CS7 0xB7000000 0x17000000 0x17000000 * ** Page C - 4 BU1 is the syste
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VSBC-32 CXC C.
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VSBC-32 CXC C.3 CPU Pinout Cross Reference The table below shows a cross reference of the special CXC released by the MC68302 and the MC68EN360.
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VSBC-32 CXC C.4 Timing Figure C-1: (E)CXC Signal Timing Legend: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Address valid to_AS, _DS _AS asserted _AS negated to R/_W invalid Data-in valid to _EDTACK _CXC-CSx asserted to AS valid _EDTACK negated to AS negated Data-in hold time _AS negated _AS, R/_W asserted to _DS asserted Data-out valid to _DS asserted _AS, _DS negated to data-out invalid A1-A7: _AS: _LDS/_UDS: R/_W: _EDTACK: _CXC-CSx: Min. Max.
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VSBC-32 CXC C.5 CXC Backplanes CXC2 C P U CXC5S CXC5 C P U STAT1 slot CS7 C P U CS CS CS CS 0 1 2 3 CS CS CS CS 0 1 2 3 CXC8S CXC8 C P U C P U STAT1 slot CS7 CS CS CS CS CS CS CS 0 1 2 3 4 5 6 CS CS CS CS CS CS CS 0 1 2 3 4 5 6 CXC8ES STAT1 slot CS7 C P U CS 0 CS 1 CS 2 CS 3 CS 4 CS 5 CS 6 Note: When using an 8TE board on the CXC5 and CXC8 backplane, one slot is lost between each board and the next. Page C - 8 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 OS-9 Cabling Appendix D OS-9 Cabling ID 21168, Rev.
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VSBC-32 OS-9 Cabling D. OS-9 Cabling This appendix outlines the connection definitions of OS-9 systems to various outside media. D.1 OS-9 System – Terminal D.1.1 Software (XON/XOFF) or No Handshake Figure D-1: 15-Pin Connector on OS-9 Side Figure D-2: 8-Pin RJ45 Connector on OS-9 Side (SMART I/O) ID 21168, Rev.
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VSBC-32 OS-9 Cabling Figure D-3: 6-Pin RJ12 Connector on OS-9 Side D.1.2 Hardware Handshake (Set Terminal to CTS/DTR Handshake) Figure D-4: 15-Pin Connector on OS-9 Side Figure D-5: 8-pin RJ45 Connector on OS-9 Side (SMART I/O) Page D - 4 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 OS-9 Cabling D.2 OS-9 System – PC D.2.1 Software (XON/XOFF) or No Handshake Figure D-6: 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side Figure D-7: 15-pin Connector on OS-9 Side, 9-pin Connector on PC Side ID 21168, Rev.
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VSBC-32 OS-9 Cabling Figure D-8: 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-Pin Connector on PC Side Figure D-9: 6-pin RJ12 Connector on OS-9 Side, 25-Pin Connector on PC Side Figure D-10: 8-Pin RJ45 Connector on OS-9 Side (SMART I/O), 9-Pin Connector on PC Side Page D - 6 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 OS-9 Cabling Figure D-11: 6-pin RJ12 Connector on OS-9 Side, 9-pin Connedctor on PC Side D.2.2 Hardware Handshake (Select RTS/CTS Handshake on the PC Side) Figure D-12: 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side Figure D-13: 15-pin Connector on OS-9 Side, 9-pin Connector on PC Side ID 21168, Rev.
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VSBC-32 OS-9 Cabling Figure D-14: 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-Pin Connector PC Side Figure D-15: 8-Pin Connector on OS-9 Side (SMART I/O), 9-Pin Connector on PC Side Page D - 8 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 OS-9 Cabling D.3 OS-9 System – Modem Figure D-16: 15-pin Connector Figure D-17: 8-pin RJ45 Connector (SMART I/O) ID 21168, Rev.
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VSBC-32 OS-9 Cabling D.4 OS-9 System – OS-9 System D.4.1 Software (XON/XOFF) or No Handshake Figure D-18: 15-pin Connector Figure D-19: 8-pin RJ45 Connector (SMART I/O) Figure D-20: 6-pin RJ12 Connector Page D - 10 © PEP Modular Computers GmbH ID 21168, Rev.
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VSBC-32 D.4.2 OS-9 Cabling Hardware Handshake Figure D-21: 15-pin Connector Figure D-22: 8-pin RJ45 Connector (SMART I/O) ID 21168, Rev.