Owner manual

VMP3 Configuration
ID 29230, Rev. 01 © 2005 Kontron Modular Computers GmbH Page 4 - 13
29230.01.UG.VC.050727/091436
P R E L I M I N A R Y
4.2.13 Serial Interrupt Mask 2 Register
The Serial Interrupt Mask Registers 1 and 2 enable the generation of a CPU interrupt. Writing
a '1' to the bit “SIRQ_ENx” enables the generation of a CPU interrupt and enables the
corresponding bit in the Serial Interrupt Pending Registers 1 and 2.
4.2.14 Serial Interrupt Polarity 1 Register
The Serial Interrupt Polarity 1 Register bits define the polarity of their corresponding serial
interrupt. A '1' written to the required bit position results in an active high sensitivity of the
corresponding interrupt and vice versa.
4.2.15 Serial Interrupt Polarity 2 Register
The Serial Interrupt Polarity 2 Register bits define the polarity of their corresponding serial
interrupt. A '1' written to the required bit position results in an active high sensitivity of the
corresponding interrupt and vice versa.
Table 4-14: Serial Interrupt Mask 2 Register
REGISTER NAME SERIAL INTERRUPT MASK 2 ACCESS
ADDRESS 0xFFFF A00F R W
BIT POSITION
MSB
7 6 5 4 3 2 1 0
LSB
CONTENT
SIRQ_EN
15
SIRQ_EN
14
SIRQ_EN
13
SIRQ_EN
12
SIRQ_EN
11
SIRQ_EN
10
SIRQ_EN
9
SIRQ_EN
8
DEFAULT
00000000
Table 4-15: Serial Interrupt Polarity 1 Register
REGISTER NAME SERIAL INTERRUPT POLARITY 1 ACCESS
ADDRESS 0xFFFF A010 R W
BIT POSITION
MSB
7 6 5 4 3 2 1 0
LSB
CONTENT
SerInt_POL
7
SerInt_POL
6
SerInt_POL
5
SerInt_POL
4
SerInt_POL
3
SerInt_POL
2
SerInt_POL
1
SerInt_POL
0
DEFAULT
00000000
Table 4-16: Serial Interrupt Polarity 2 Register
REGISTER NAME SERIAL INTERRUPT POLARITY 2 ACCESS
ADDRESS 0xFFFF A011 R W
BIT POSITION
MSB
7 6 5 4 3 2 1 0
LSB
CONTENT
SerInt_POL
15
SerInt_POL
14
SerInt_POL
13
SerInt_POL
12
SerInt_POL
11
SerInt_POL
10
SerInt_POL
9
SerInt_POL
8
DEFAULT
00000000