Manual

VMP2 Functional Description
ID 24855, Rev. 02Page 2 - 6 © 2002 PEP Modular Computers GmbH
2.4 Main Features
The following descriptions provide an overview of the main features of the principal func-
tional blocks of the VMP2.
2.4.1 CPU
The VMP2 is based on the Motorola PowerPC processor MPC8245 which integrates a
large number of peripherals, such as a PCI interface, PCI arbiter, Interrupt Controller,
Memory Controller and multiple Timers. CPU speed is 330 MHz.
2.4.1.1 MPC8245 (Kahlua II) Features
Important features of the MPC8245 implemented on the VMP2 are as follows:
Peripheral logic
Memory interface
• Programmable timing supporting SDRAM (The VMP2 uses SDRAM at 132
MHz)
• High bandwidth bus (64-bit data bus) to SDRAM
• 2 memory banks with up to 128 MByte each
• Supports 64, 128 and 256 Mbit SDRAM
• Contiguous memory mapping
• 8-bit ROM interface
• Write buffering for PCI and processor accesses
• Supports ECC
• SDRAM data path buffer
• Low voltage transistor-to-transistor logic (LVTTL)
• Port X: 8-bit general-purpose I/O port using ROM controller
interface with address strobe
32-bit PCI interface operating up to 33 MHz on the VMP2
• PCI Specification Revision 2.1 compatible
• PCI 5.0-V tolerance
• Support for PCI-locked accesses to memory
• Support for accesses to all PCI address spaces
• Selectable big- or little-endian operation
• Store gathering of processor-to-PCI write and PCI-to-memory write accesses
• Memory prefetching of PCI read accesses
• Selectable hardware-enforced coherency
• PCI bus arbitration unit (five request/grant pairs)