VMP1 Power PC-based CPU Board for VME Applications Manual ID 19972, Rev. Index 0101 Apr 00 The product described in this manual is in compliance with all applied CE standards.
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VMP1 Preface Table of Contents Preface Manual Table of Contents...................................................................................... 0 - 3 Revision History ................................................................................................... 0 - 10 Trademarks.......................................................................................................... 0 - 10 Explanation of Symbols ...................................................................................
Preface Chapter VMP1 2 Functional Description ..................................................................... 2 - 3 2.1 Functional Block Diagram ............................................................................. 2 - 3 2.2 Front Panels .................................................................................................. 2 - 4 2.3 Board Layout ................................................................................................. 2 - 5 2.4 Main Features ............
VMP1 Chapter Preface 3 Installation....................................................................................................3 - 3 3.1 Board Installation ...........................................................................................3 - 3 3.1.1 Front Panel I/O Connectors ......................................................................3 - 4 Chapter 4 Configuration.............................................................................................4 - 3 4.
Preface VMP1 4.3.4.9 Control Register ................................................................................. 4 - 13 4.3.4.10 Event Register ................................................................................. 4 - 13 4.3.4.11 Board / Logic Revision Register ...................................................... 4 - 14 4.3.4.12 UART A / Registers .......................................................................... 4 - 15 4.3.4.13 UART B / Registers .............................
VMP1 Appendix Preface A VMP1-IO1 Module (Optional) ...................................................... A - 3 A Overview ........................................................................................................ A - 3 B Board Interfaces ............................................................................................. A - 4 C Board Layout .................................................................................................. A - 5 D Front Panel .....................
Preface VMP1 Figures Figure Number and Title 2-1 Functional Block Diagram ............................................................................. 2 - 3 2-2 Front Panels .................................................................................................. 2 - 4 2-3 VMP1 Board (Front View) ............................................................................. 2 - 5 2-4 VMP1 Board (Rear View) ..............................................................................
VMP1 Preface 2-3 Serial Port RJ45 Pin Assignment ................................................................2 - 12 2-4 PCI Expansion Connector Pinout ................................................................2 - 13 2.5 Serial Interface Expansion Connector (CON3) Pinout .................................2 - 15 2.6 Debug Interface Connector (CON10) Pinout................................................2 - 16 2-7 Watchdog Time Values .................................................................
Preface VMP1 Revision History Revision History Manual/Product Title: VMP1 Manual ID Number: 19972 Rev. Index Brief Description of Changes Board Index Date of Issue 0100 Initial Issue 01 Mar. 00 0101 Correction to Table 4-1, page 4-3 01 Apr. 00 This document contains information proprietary to PEP Modular Computers.
VMP1 Preface Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Please see also the section “Applied Standards” in this manual. Caution! This symbol and title warn you of hazards due to electrical shocks (> 60 V) when touching products or parts of them. Failure to observe the necessary precautions as described and/or prescribed by the law may result in damage to your product and/or endanger your life/health.
Preface VMP1 For your safety Your new PEP product has been developed and carefully tested in order to provide all the features necessary to ensure full compliance with all electrical safety requirements. It has also been designed for a long fault-free life. However, the life expectancy of your product will be drastically reduced by improper treatment during unpacking and installation.
VMP1 Preface General Instructions on Usage $ In order to maintain PEP’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by PEP Modular Computers and described in this manual or received from PEP Technical Support as a special handling instruction, will void your warranty.
Preface VMP1 Two Year Warranty PEP Modular Computers grants the original purchaser of a PEP product a TWO YEAR LIMITED as described in the following. However, no other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the customer has the express written consent of PEP Modular Computers.
VMP1 Introduction Chapter 1 Introduction 1.1 Board Introduction ............................................................... 1 - 4 1.2 Board Overview ................................................................... 1 - 5 1.3 VMP1 Main Specifications ................................................... 1 - 6 1.4 Applied Standards ............................................................... 1 - 8 1.4.1 CE Compliance ........................................................... 1 - 8 1.4.
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VMP1 Introduction 1. Introduction The VMP1 is a comprehensive computing platform which brings togethor the latest advances in computing technology in a board designed for maximum performance, flexibility and versatility within a rugged compact format. The design centered on realizing a board which addresses the need for increased computing capacity while at the same time reducing the size and number of system components in order to reduce space requirements and optimize power dissipation.
VMP1 Introduction 1.1 Board Introduction The VMP1 is a VME PowerPC-based single-board computer specifically designed for use in highly integrated platforms with solid mechanical interfacing for a wide range of industrial environment applications.
VMP1 Introduction 1.2 Board Overview The VMP1 is a 3U VME CPU board featuring a powerful CPU (number cruncher). The design is based on the new highly integrated Motorola PowerPC processor MPC8240, which integrates a PCI interface and several peripherals inside one Chip. Two standard memory configurations (32 MB or 64 MB SDRAM) are available, with 128 MB available on request. Flash memory for integrating the initial bootloader and ROMable operating systems are provided .
VMP1 Introduction 1.
VMP1 Introduction Table 1-1: VMP1 Main Specifications VMP1 Specifications Debug Interface JTAG/BDM VME Connector 96-pin VME connector Onboard Connectors 2 x RJ45 for RS232, 1 x RJ45 for Ethernet PCI Expansion Modules PMC carrier, future PCI based I/O board with VGA/SCSI/2 nd Ethernet Mechanical Conformance Conforms with IEEE 1101.10 Power Supply 5V in accordance with the VME Specification, 1.
VMP1 Introduction 1.4 Applied Standards 1.4.1 CE Compliance The PEP Modular Computers’ VME systems comply with the requirements of the following CE-relevant standards: • • • Emission Immission Electrical Safety 1.4.2 • EN50081-1 EN50082-2 EN60950 Mechanical Compliance Mechanical Dimensions 1.4.3 IEEE 1101.10 Environmental Tests • Vibration Random Vibration, Broadband IEC68-2-6 IEC68-2-64 (3U boards) • • Permanent Shock Single Shock IEC68-2-29 IEC68-2-27 1.5 Related Publications 1.5.
VMP1 Functional Description Chapter 2 Functional Description 2.1 Functional Block Diagram .................................................... 2 - 3 2.2 Front Panels ........................................................................ 2 - 4 2.3 Board Layout ....................................................................... 2 - 5 2.4 Main Features ..................................................................... 2 - 6 2.4.1 CPU ...............................................................
VMP1 Functional Description Functional Description 2.5.2 RTC (STC M41T56) .................................................. 2 - 18 2.5.3 Reset/Abort ............................................................... 2 - 18 2.5.4 Front Panel LED’s ..................................................... 2 - 19 ID 19972, Rev.
VMP1 Functional Description 2. Functional Description 2.
VMP1 Functional Description 2.2 Front Panels Figure 2-2: Front Panels U W RST H AB U W RST H AB Standard VMP1 and Standard with IO1 Module LNK. ACT. LNK. SPEED ACT. VMP1 SPEED VMP1 VMP1-IO1 KEY LED colors (for B&W monitors and printouts): U = green W = yellow H = red U W RST H AB U W RST LNK. ACT. VMP1 Page 2 - 4 H AB VMP1 Optoisolated version and Optoisolated version with IO1 Module - note the different position of the SER 0 connector LNK. SPEED ACT.
VMP1 Functional Description 2.3 Board Layout Figure 2-3: VMP1 Board (Front View) J1 1 LED SDRAM MEMORY BANK 1 GND ABORT & RESET RTC UART RJ45 (Serial) X BUS BUFFERS DC/DC DC/DC RJ45 (Term.) LOGIC LED 11 12 1 2 ETHERNET PCI TO VME BRIDGE CPU ETHERNET 2 CON10 16 1 1 JTAG 15 2 99 GOLDCAP CON11 PCI EXPANSION CONNECTOR 100 BATTERY (Optional) Figure 2-4: VMP1 Board (Reverse View) R3 R8 R7 R6 SDRAM MEMORY BANK 2 R13 R12 R11 MAGNIFIED R3 R8 R7 R6 R13 R12 R11 ID 19972, Rev.
VMP1 Functional Description 2.4 Main Features The following descriptions provide an overview of the main features of the principal functional blocks of the VMP1. 2.4.1 CPU The VMP1 is based on the Motorola PowerPC processor MPC8240 which integrates a large number of peripherals, such as a PCI interface, PCI arbiter, Interrupt Controller, Memory Controller and multiple Timers. CPU speed is 250 MHz. 2.4.1.
VMP1 Functional Description PCI agent mode capability • • • • • • • • • • Address translation unit Internal configuration registers accessible from PCI Two-channel integrated DMA controller Supports direct mode or chaining mode (automatic linking of DMA transfers) Supports scatter gathering - read or write discontinuous memory Interrupt on completed segment, chain, and error Local-to-local memory PCI-to-PCI memory PCI-to-local memory Local-to-PCI memory Message unit • • • I2O message controller Two doo
VMP1 2.4.2 Functional Description Memory 2.4.2.1 System Memory (DRAM) The main memory of the VMP1 consists of 32 MB or 64 MB SDRAM (128 MB available on request) soldered onto the board for mechanical stability. The VMP1 provides ECC support (optional) and a maximum memory speed of 100MHz. 2.4.2.2 Flash 4 or 8 MB of soldered Flash memory accommodate the bootstrap loader software and can be used to store ROMable operating systems or user data.
VMP1 2.4.3 Functional Description Board Interfaces 2.4.3.
VMP1 Functional Description VME Bus Connector Pinout Table 2-1: Pin Assignment J1/P1 VME Pin Number Pinrow A Pinrow B Pinrow C 1 D00 BBSY D08 2 D01 BCLR D09 3 D02 ACFAIL D10 4 D03 BG0IN D11 5 D04 BG0OUT D12 6 D05 BG1IN D13 7 D06 BG1OUT D14 8 D07 BG2IN D15 9 GND BG2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AM0 A22 17 GND AM1 A21 18 AS AM2 A20 19
VMP1 Functional Description 2.4.3.2 Ethernet Connector and Pinout 1 The Ethernet interface is based on a PCI device from Intel; the Ethernet Controller 82559ERS. 8 The main features of the Ethernet are as follows: • • • • • • integrated IEEE 802.3 10Base T and 100Base TX compatible PHY glueless 32-bit PCI master interface compatible with driver software of the 82558 and 82557 full duplex support at both 10 and 100 Mbps IEEE 802.
VMP1 Functional Description 2.4.3.3 Serial Interfaces and Pinouts 1 Two serial ports (RS232) are provided by means of two 8-pin RJ45 connectors. 8 The RS232 serial interfaces named TERM and SER are 16C550 compliant and have 128-byte transmit and receive buffers. In addition to their other uses, the TERM port is used to interface with the bootstrap loader and the SER port is used to download software.
VMP1 Functional Description 2.4.3.4 PCI Expansion Connector and Pinout Figure 2-5: PCI Expansion Connector 1 CON11 PCI EXPANSION CONNECTOR 2 99 100 The PCI Expansion Connector provides the possibility to mount several transition boards above the VMP1 for adding special functionality which is not provided on the VMP1 main board or on the VME bus. All the PCI signals of the onboard PCI bus will be routed to this connector, so that a complete PCI bus is provided on this connector.
VMP1 Functional Description PCI Expansion Connector (CON11) Pinout Table 2-4: PCI Expansion Connector Pinout Signal GND Pin Number Pin Number Signal 1 2 SCL (I2C) 3 4 +3.3V 5 6 CLK2 CLK3 7 8 GND GND 9 10 CLK4 INTB# 11 12 INTA# INTD# 13 14 INTC# +5V 15 16 GNT#2 GNT#3 17 18 +5V +3.
VMP1 Functional Description Table 2-4: PCI Expansion Connector Pinout Signal Pin Number Pin Number Signal PERR# 67 68 +5V SERR# 69 70 GND +5V 71 72 PAR C/BE1# 73 74 AD15 AD14 75 76 +3.3V GND 77 78 AD13 AD12 79 80 AD11 AD10 81 82 GND GND 83 84 AD9 AD8 85 86 C/BE0# AD7 87 88 +5V +3.
VMP1 Functional Description 2.4.3.5 Serial Interface Expansion Connector and Pinout The serial interface expansion connector provides the capability to add different front end interfaces to the UART B signals. For example, an opto-isolated RS422/485 module (currently under development) may be plugged onto this connector.
VMP1 Functional Description 2.4.3.7 DEBUG Interface and Pinout A JTAG/BDM interface is provided on the VMP1 for software debugging. The pinout of this connector is in accordance with the pinout of the most commonly used emulator probes. $ 2 CON10 16 1 JTAG 15 Note: As shipped, only the Altera onboard logic may be detected by means of the JTAG interface. If the JTAG interface requires to be re-configured for software debugging, please contact Support at PEP Modular Computers for assistance.
VMP1 Functional Description 2.5 Special Board Features 2.5.1 Watchdog Timer A watchdog timer is provided, which forces an NMI or Reset condition (configurable in the watchdog register). The watchdog time can be programmed in 4 steps with a resolution of 500 ms. If the watchdog timer is enabled, it cannot be stopped or reprogrammed. Table 2-7: Watchdog Time Values Watchdog Time Values 500 ms 1s 1.5s 2s 2.5.2 RTC (STC M41T56) The Real Time Clock provides the following features: • • • • • • • • • 2.5.
VMP1 2.5.4 Functional Description Front Panel LED’s Three LED’s with the colors red, green and yellow are provided on the front panel (please see Figure 2-2 on page 2-4) to give a quick indication of several key operating conditions: • • • The red LED (H) is general purpose. The yellow LED (W) indicates WATCHDOG ACTIVE The green LED (U) has been preset to light on initialisation of the board.
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VMP1 Installation Chapter 3 Installation 3.1 Board Installation ................................................................. 3 - 3 3.1.1 ID 19972, Rev. 0101 Front Panel I/O Connectors ........................................
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VMP1 Installation 3. Installation The VMP1 has been designed for easy installation. However, the following importantstandard precautions must be observed. Some other important information is also set out below. 3.1 Board Installation Slot Selection The VMP1 is designed so that it may be used in any free slot of a 3U VME Backplane. It has an automatic first slot detection mechanism which configures it as a System Controller when placed in the far left slot.
VMP1 Installation ESD Equipment! Your VMP1 board contains electrostatically sensitive devices. Please observe the necessary precautions to avoid damage to your board: • Discharge your clothing before touching the assembly. Tools must be discharged before use. • Do not touch components, connector-pins or traces. • If working at an anti-static workbench with professional discharging equipment, please do not omit to use it. PEP Advantage The VMP1 is designed to be bootstrapped from the Flash device alone.
VMP1 Configuration Chapter 4 Configuration 4.1 Jumper Settings .................................................................. 4 - 3 4.1.1 Bootstrap Loader / Socket Jumper J1 ......................... 4 - 3 4.1.2 RTC (Real-time clock) Calibration OutputJ2 ............... 4 - 3 4.1.3 Resistor Setting for Non-standard Socket Devices ..... 4 - 4 4.1.4 RS485 Termination (Onboard Interface Only) ............ 4 - 4 4.2 Pinouts ........................................................................
VMP1 Configuration Configuration 4.3.4.9 Control Register .................................................. 4 - 13 4.3.4.10 Event Register .................................................... 4 - 13 4.3.4.11 Board / Logic Revision Register ......................... 4 - 14 4.3.4.12 UART A / Registers ............................................. 4 - 15 4.3.4.13 UART B / Registers ............................................. 4 - 16 4.3.5 IRQ Routing .......................................................
VMP1 Configuration 4. Configuration 4.1 Jumper Settings Please see Figures 2-3 and 2-4 in Chapter 2 to view the positions of the jumpers and resistors on the board. 4.1.1 Bootstrap Loader / Socket Jumper J1 The Jumper J1 is used to select the memory position from which the VMP1 fetches its boot code. It determines the address position of the onboard Flash window and the Flash/SRAM expansion socket (DIL600, 32-pin).
VMP1 4.1.3 Configuration Resistor Setting for Non-standard Socket Devices The default pinout of this socket is designed for use with standard DIL Flashes and MSystems DiskOnChip.
VMP1 Configuration 4.2 Pinouts 4.2.1 Flash Socket Type Selection 4.2.1.1 Socket Device Selection (Memory Expansion Socket IC8) A range of different memory devices may be used on the DIL32 socket (e.g. Flashes, NVSRAM, M-Systems Disk-On-Chip, EPROM etc.).
VMP1 Configuration 4.2.2 Serial Interface Expansion Connector (CON3) Table 4-5: RS Expansion Connector Pinout Pin Number Function Function Pin Number 1 GND RTSB 2 3 RE DE 4 5 RxD TxD 6 7 CTS DTR 8 9 SCL SDA 10 11 +3.3V VCC 12 Page 4 - 6 ® PEP Modular Computers GmbH ID 19972, Rev.
VMP1 Configuration 4.3 Board Address Map 4.3.1 Address Map Overview Figure 4-1: VMP1 Address Map, 2 MB 8-bit Bank 0xFFFF FFFF 0xFEC0 0000 BANK0 Reset Entry 0xFFE0 0000 0xFFF0 0100 0xFFE0 0000 mirror Bank 0 PCI / VME 0xFF80 0000 unusable 0x8000 0000 RESERVED 0x4000 0000 DRAM 0x0000 0000 ID 19972, Rev.
VMP1 4.3.2 Configuration VME Address Area Figure 4-2: VME Address Area 0x8FFF FFFF currently unused 0x8800 0000 VME A24/D16 0x8700 0000 currently unused 0x8501 0000 VME A16/D16 0x8500 0000 currently unused 0x8400 0000 VME USER2 0x8300 0000 VME USER1 0x8200 0000 currently unused 0x8000 0000 VME bus slave address and VME IRQ mask are programmable inside the TUNDRA UNIVERSE II. Please refer to the VME slave manual chapter in the TUNDRA UNIVERSE II manual and the BSP documentation.
VMP1 Configuration 4.3.
VMP1 Configuration 4.3.4 Special Registers Overview The Special Registers may be attached through read and write operation to the address space FFe8 0000-FFF0 0000 4.3.4.
VMP1 Configuration 4.3.4.4 Memory Configuration Register Table 4-9: Memory Configuration Register • • • • Register Address Memory Configuration FFe0 0014 MSB BJ 6 5 4 3 2 1 LSB Res. Res. ECC Res. Res. SZ1 SZ0 Bits SZ0 and SZ1 are used to identify the soldered SDRAM size. Bit 2 and Bit 3 are reserved Bit 4 (ECC) is used to indicate that ECC is supported (1 = ECC enabled) Bit MSB (BJ) indicates the status of the BOOT JUMPER (jumper J1 for exchanging Socket and Flash Chip Select).
VMP1 Configuration 4.3.4.7 Watchdog Control Register Table 4-12: Watchdog Control Register Register Watchdog control Address MSB 6 5 4 3 2 1 LSB FFe0 0018 WD_EN WD_R Res. WD_TRG Res. Res. WDT1 WDT0 4.3.4.8 Watchdog Timeout Time Bits WDT0 and WDT1 are programmed to select the Watchdog timeout value. Table 4-13: Watchdog Timeout Time WDT1 WDT0 Time 0 0 0,5s 0 1 1s 1 0 1,5s 1 1 2s • • • • • Page 4 - 12 Bits 2 and 3 are reserved Bit WD_TRG retriggers the watchdog timer.
VMP1 Configuration 4.3.4.9 Control Register Table 4-14: Control Register Register Control • • • • • Address MSB FFe0 001a RS_CTL 6 5 Res. Res. 4 S_RST 3 2 Res. Res.
VMP1 Configuration 4.3.4.11 Board / Logic Revision Register Table 4-16: Board / Logic Revision Register Register Address Board revision FFE0 001e MSB LR3 6 5 4 LR2 LR1 LR0 3 BR3 2 BR2 1 BR1 LSB BR0 The Board Revision Register may be used to identify the hardware and logic status of the board by the software. It starts with the value 0x00 for the initial board prototypes and will be incremented with each redesign / logic release. • Page 4 - 14 This register is READ ONLY.
VMP1 Configuration 4.3.4.12 UART A / Registers For a detailed description please refer to the EXAR XR16C 2850 DUART manual.
VMP1 Configuration 4.3.4.13 UART B / Registers For a detailed description please refer to the EXAR XR16C 2850 DUART manual The UART B occupies the following addresses:.
VMP1 4.3.
VMP1 4.3.6 Configuration Real-time Clock Access to the RTC is effected via the I2C bus. The RTC uses address 0xD0 For more detailed information please refer to the manuals for the ST - Microelectronics M41T56 and the Motorola MPC 8240 (I2C - Bus).
VMP1 4.3.7 Configuration EEPROM Access to the EEPROM is effected via the I2C bus of the MPC8240. The EEPROM uses the I2C address 0xA0. For more detailed information please refer to the manuals for the MICROCHIP 24LC16B and the MOTOROLA MPC8240 (I2C bus). 4.3.8 Digital Temperature Sensor Access to the onboard temperature sensor is effected via the I2C bus of the MPC8240. The EEPROM uses the I2C address 0x90.
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VMP1 Bootstrap Loader Chapter 5 Bootstrap Loader 5.1 System Operation ................................................................ 5 - 3 5.1.1 Startup ........................................................................ 5 - 3 5.1.2 Entering the Command Mode ..................................... 5 - 4 5.1.3 Programming a New Binary Image to Flash ............... 5 - 4 5.1.4 BootWaitTime ............................................................. 5 - 8 5.1.
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VMP1 Bootstrap Loader 5. Bootstrap Loader The VMP1 Bootstrap Loader is a standalone software located in the Flash memory which allows the user to safely update the contents of the Flash and delay the boot process for a specified time. The Bootstrap Loader has the capability to program Flash memory from “MOTOROLA S-RECORDS” or from an absolute memory address. If the programmed image does not work, the Bootstrap Loader can be re-entered.
VMP1 Bootstrap Loader 5.1.2 Entering the Command Mode There are two possible reasons for entering the Bootstrap Loader command mode: • If no valid start key is found, the Bootstrap Loader command mode is entered automatically. If the user wants to enter the Bootstrap Loader manually, e.g. for re-programming the Flash contents, the ABORT button on the front panel must be used.
VMP1 Bootstrap Loader Programming with Motorola S-Records Programming is done with the If command. The If command accepts S1, S2 and S3 records. Operation is terminated by the appropriate S9, S8 or S7 record. Other types of records are ignored. The checksum of every record except end records is checked. Bad records are rejected by the Bootstrap Loader. The address range of every record is also checked; records that try to overwrite the Bootstrap Loader are rejected.
VMP1 Bootstrap Loader Monitoring the Programming Progress In both examples, the programming can be monitored via the term port. The characters which are displayed have the following meaning: • • • • • r t e c p Read S-record; valid and in range Protected sector touched Erase sector Copy to buffer, program later Program record None of the above characters indicate an error.
VMP1 Bootstrap Loader Programming from an Absolute Address The second way to program Flash memory is to program it from an absolute address. The image to be programmed must be located in a visible address range, for example on the VMEbus. A memory card with battery-backup, Flash or EPROM can be used to hold the image to program.
VMP1 Bootstrap Loader 5.1.4 BootWaitTime The command bw can be used to display/change the current BootWaitTime. Available delays are 1-2-5-10-20-50 seconds. CPU’s without a user LED or without an ABORT button have a BootWaitTime of at least 5 seconds. In this case, the Bootstrap Loader will reject a BootWaitTime setting of 1-2 seconds. The BootWaitTime value is stored in the boot section of the serial EEPROM. This section is validated with a CRC code to avoid the setting of random parameters.
VMP1 5.1.5 Bootstrap Loader Example Using Hyperterminal under Windows 95/Windows NT The host is assumed to be a PC with Windows 95 or Windows NT. A serial cable is used to connect the term port of the board to be programmed to COM2 of the PC. Additionally, we assume that we want to program a MOTOROLA S-record built for the Flash address of the board. The serial connection runs at the default configuration of 9600 Baud with no parity and one stop bit.
VMP1 Bootstrap Loader Enter 'lf' on the target. The target now waits until the MOTOROLA S-records have been transferred over the term. Select Transfer/Send Text File dialogue box and select the file containing the MOTOROLA S-records. Figure 5-3: Select Transfer/Send Text File Dialogue Box Figure 5-4: Selecting the MOTOROLA S-Records File After selecting Open the dialogue box disappears and the MOTOROLA S-records are transferred.
VMP1 Bootstrap Loader 5.2 Commands 5.2.1 Boot Wait Syntax bw [
VMP1 5.2.3 Bootstrap Loader Memory Display Syntax md [] Description Without parameters specified, the Flash contents starting at the beginning of the programmable Flash area are displayed. This function is not limited to Flash and other address ranges can be specified. $ Page 5 - 12 Important! The first instruction to be executed in Flash is not identical to the one to be executed first from the programming source (Srecords memory block). ® PEP Modular Computers GmbH ID 19972, Rev.
VMP1 Bootstrap Loader 5.2.4 Port Format Syntax pf [ [][/[][/[][/]]]] Description Without parameters specified, the current serial port settings are displayed. • • • • • specifies the serial port. Valid values are term or ser0. specifies the baud rate. The values 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800, 7200, 9600, 19200, 38400 and 115200 Baud can be specified. specifies the bits / character.
VMP1 5.2.5 Bootstrap Loader Reset System Syntax rs Description This command exits the Bootstrap Loader and resets the system. It terminates the Bootstrap Loader command mode and resets the entire system, generating a system reset with the onboard watchdog. 5.2.6 Help Syntax ? or help Description This command prints the online help page. The display of the help text varies between the different CPU’s reflecting their differences. 5.2.
VMP1 Bootstrap Loader 5.4 Porting an Operating System to the VMP1 The image for the absolute address 0×0 should be linked with an entry point at the absolute address at 0×100. One should not attempt to reassign the PCI BAR registers. The assigned values should be read back and these should always be used in the drivers. The “interrupt line” field in the PCI configuration header is initialized with the IRQ line number to which the INTA of the device is routed.
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VMP1 VMP1-IO1 Module (Optional) Appendix A VMP1-IO1 Module (Optional) A Overview ............................................................................... A - 3 B Board Interfaces .................................................................... A - 4 C Board Layout ......................................................................... A - 5 D Front Panel ............................................................................ A - 6 E Technical Specifications ...................
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VMP1 VMP1-IO1 Module (Optional) VMP1-IO1 Module (Optional) A Overview The PEP VMP1-IO1 module has been designed to provide the VMP1 user with an effective gateway to the world of PMC modules. This additional capability opens up the broadest range of expansion possibilities. PMC modules are renowned for their flexibility and versatility of use. They afford the user wide ranging system-independent solutions by means of easily interchanged or upgraded mezzanine add-on modules.
VMP1 B VMP1-IO1 Module (Optional) Board Interfaces PCI Expansion Connector The PCI expansion connectors CON2/CON3 provides all the necessary signals for data transfer as defined by PCI Specification Rev. 2.1. PMC Interface The PMC interface provides an easy way to extend the VMP1 via the wide array of interfaces and functions which are available on PMC modules produced by the entire range of PMC vendors.
VMP1 C VMP1-IO1 Module (Optional) Board Layout The VMP1-IO1 has two onboard connectors (CON9 and CON10) which provide all the PCI signals and the power supply for the PMC module. Figure A-1: Board Layout (Front View) 1 2 1 2 MAGNIFIED 63 DC/DC 1 2 ID 19972, Rev.
VMP1 D VMP1-IO1 Module (Optional) VMP1-IO1 Front Panel Figure A-2: VMP1-IO1 Front Panel VMP1-IO1 The VMP1-IO1 front panel is provided with a window for the insertion of a PMC module bezel. Page A - 6 ® PEP Modular Computers GmbH ID 19972, Rev.
VMP1 E VMP1-IO1 Module (Optional) Technical Specifications Table A-1: VMP1-IO1 Specifications VMP1-IO1 Specifications PCI-Standard Compliant with PCI 2.1 Signaling Voltage PMC-Side: 5V signaling Connectors PMC Jn1 (CON4) and Jn2 (CON5) connectors Mechanical Compliance IEEE 1101.10 CMC IEEE P1386/Draft 2.
VMP1 F VMP1-IO1 Module (Optional) Board Installation In order to keep the installation process as simple and easy as possible please follow the recommended order of work: 1. Instal the PMC module on the VMP1-IO1 2. Instal the package, VMP1-IO1 plus PMC module, on the baseboard (in this case the VMP1) ESD Equipment! Your carrier board and PMC module contain electrostatically sensitive devices.
VMP1 VMP1-IO1 Module (Optional) Figure A-3: Installation Diagrams PMC module VMP1-IO1 Front Panel 2 1 VMP1-IO1 PMC bezel 10mm stand-off 3 4 *M2.5 *6mm screws ID 19972, Rev.
VMP1 G VMP1-IO1 Module (Optional) Pinouts G1 Jn1 (CON4) Pin Assignment Table A-2: Jn1, 32-bit PCI Pin Number Signal Name Signal Name Pin Number 1 TCK -12V 2 3 Ground INTA# 4 5 INTB# INTC# 6 7 BUSMODE1# +5V 8 9 INTD# PCI-RSVD* 10 11 Ground PCI-RSVD* 12 13 CLK Ground 14 15 Ground GNT# 16 17 REQ# +5V 18 19 V(I/O) AD[31] 20 21 AD[28] AD[27] 22 23 AD[25] Ground 24 25 Ground C/BE[3]# 26 27 AD[22] AD[21] 28 29 AD[19] +5V 30 31 V(I/O) AD[17] 32
VMP1 G2 VMP1-IO1 Module (Optional) Jn2 (CON5) Pin Assignment Table A-3: Jn2, 32-bit PCI Pin Number Signal Name Signal Name Pin Number 1 +12V TRST# 2 3 TMS TDO 4 5 TDI Ground 6 7 Ground PCI-RSVD* 8 9 PCI-RSVD* PCI-RSVD* 10 11 BUSMODE2# +3.3V 12 13 RST# BUSMODE3# 14 15 3.3V BUSMODE4# 16 17 PCI-RSVD* Ground 18 19 AD[30] AD[29] 20 21 Ground AD[26] 22 23 AD[24] +3.3V 24 25 IDSEL AD[23] 26 27 +3.
VMP1 H VMP1-IO1 Module (Optional) Jumper Setting The jumper settings of the IO1 module depend on the module’s position relative to the VMP1 and other modules, if any (please see Figure A4 below).
VMP1 VMP1-Post (Optional) Appendix B VMP1-Post (Optional) VMP1-Post ................................................................................... B - 3 ID 19972, Rev.
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VMP1 VMP1-Post (Optional) VMP1-Post (Optional) Board description The VMP1-Post is an optionally available tool which is used for hardware and software debugging. During the startup process of the VMP1 it provides the user with information about the status of the boot process by means of a message code similar to the post codes on the Intel PC. Please note that a Postcode reference list setting out the meanings of the number codes is available from the local sales office .
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VMP1 Optoisolation RS485 Module (Optional) Appendix C Optoisolation RS485 Module (Optional) Optoisolation Module ...................................................................C - 3 ID 19972, Rev.
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VMP1 Optoisolation RS485 Module (Optional) Optoisolation RS485 Module (Optional) Board description On the VMP1 it is possible to utilize a transition module which provides optoisolated RS485 functionality (half and full duplex). Users who require an optoisolated version of the VMP1 are supplied with a customized VMP1 on which the standard RJ45 connector is omitted and also with this module which comes with a substitute RJ45 connector routed through optoisolation circuitry on the module.
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VMP1 JTAG Subsystem Appendix D JTAG Subsystem JTAG Chain .................................................................................D - 3 ID 19972, Rev.
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VMP1 JTAG Subsystem JTAG Subsystem Description All the JTAG capable devices on the VMP1 can be accessed through the onboard JTAG chain. The factory setting of the chain is such that only the onboard logic is in the chain. If it is required to access the Processor via the JTAG chain a different setting must be used (some resistors must be reset). The following picture illustrates the construction of the JTAG chain. Figure D-1: JTAG Chain Illustration 3.
VMP1 JTAG Subsystem If EMULATOR access to the MPC8240 is required it must be ensured that R94 and R183 are set and also that R104 and R180 are removed (all resistors are 0R).
