Manual

VM62(A) / VM42(A) User’s Manual Chapter 6 Software Configuration

6. SOFTWARE CONFIGURATION

6.1 Initializing the 68EN360

Many components of the VM62(A) / VM42(A) are controlled by the MC68EN360. Due to this fact, this chip requires a

special initialization sequence before any other software can be started.

The following list describes how the initialization must be performed on the VM62(A) / VM42(A).

WARNING!

The order of the initialization listed below must not be changed, otherwise erratic

behaviour of the board may result.

1) Set DPRBASE to 0x000000 0x7000001.L -> MBAR (in CPU space!)

Example

move.l #7,d1 select CPU space

move.l #$7000001,d0 value to write to MBAR

movec d1,dfc select CPU space

moves.l d0,MBAR set MBAR

2) Clear reset status register 0xFF.B -> RSR

3) Set system protection register

• bus monitor enabled, 128 system clocks timeout 0x7.B -> SYPCR

4) Set module configuration register

• bus request MC68040 arbitration ID: 3

• arbitration synchronous timing mode

• bus clear out arbitration ID: 3

• SIM60 registers are Supervisor Data

• BusClear in arbitration ID: 3

• interrupt arbitration: 3 0x60008CB3.L -> MCR

5) Set PLL enabled and lock access 0xC000.W -> PLLCR

6) Lock access to clock divider control register 0x8000.W -> CDVCR