Manual

Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual
2.3.3 Mailbox Interrupt
An external VMEbus master may interrupt the VM62(A) / VM42(A) by setting P_IRQ5 (pending mailbox IRQ) in the
VME control / status register. The address of this dual-ported register seen from VME is identical to the base address of
the dual-ported SRAM, occupying the lower 8 kBytes (odd byte addresses) of the dual-ported SRAM.
Setting P_IRQ5 generates an autovector 5 interrupt on the CPU. Typically, the on-board CPU resets P_IRQ5 during the
processing of the corresponding interrupt service routine.
Note
Although every odd address of the 8k block of the VME control / status register can be accessed from
VME, only the P_IRQ5 bit can be set. All other bits are write protected from the VME. As the
P_IRQ5 bit is located at bit 7 within the register, it can be directly used as a semaphore because read-
modify-write (TAS instruction) is supported.
2.3.4 VMEbus Control / Status Register
Address: CS7 + $5 PEP Default Address $CD 00 00 05
Format: Byte
Access: read / write
Value after HW reset: see table
BADR2BADR3 BADR1 BADR0
CS7 + $5
01234567
P_IRQ5 FSDEN_BERR2EN_DPR
Register Description
Name Value Reset (HW) Reset PEP (SW) Description
Slot 1 Other Slot 1 Other
P_IRQ5
bit 7
1 0 0 0 0 Pending mailbox IRQ
EN_DPR
bit 6
1 0 0
Value
stored in
EEPROM
Value
stored in
EEPROM
Dual-port RAM (including mailbox
IRQ) for VME requester enabled. Base
address fixed through BADRx bits
EN_BERR2
bit 5
1 0 0 1 0 Enable bus monitor timer, all VME
cycles, timeout after 128µs
FSD
bit 4
1 1 0 1 0 VMEbus ‘First Slot Detection’ flag,
system controller
BADR3
- BADR0
bits 3 - 0
0 0
Value
stored in
EEPROM
Value
stored in
EEPROM
VME address location of dual-ported
RAM. Equivalent to VME address lines
A23 - A20, programmable from $0 - $F
in 1 Mbyte windows, enabled with
EN_DPR. See Table on next page.
Page 2-6 © 1995 PEP Modular Computers May 17, 1996