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Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual

2.2.5 Address Map

The VM62(A) / VM42(A) address map shown in the Table below is based on the recommended default initialisation of

the 68EN360 chip select logic.

Figure 2.2.5.1: VM62(A) / VM42(A) Address Map (PEP Default)

Address (Hex) Device

00 xx xx xx

04 xx xx xx

07 00 0x xx

09 xx xx xx

0A xx xx xx

0B xx xx xx

0C xx xx xx

0D xx xx xx

1x xx xx xx

2x xx xx xx

3x xx xx xx

4x xx xx xx

5x xx xx xx

6x xx xx xx

82 xx xx xx

83 xx xx xx

85 00 xx xx

87 xx xx xx

9x xx xx xx

Ax xx xx xx

Bx xx xx xx

C0 xx xx xx

C4 xx xx xx

C7 xx xx xx

CA xx xx xx

CB F7 0x xx

CC xx xx xx

CD 00 00 01

CD 00 00 05

CD 00 00 07

Dx xx xx xx

Ex xx xx xx

Fx xx xx xx

DRAM (68EN360’s CS1)

FLASH (68EN360’s CS0)

Reserved, 68EN360 internal RAM / register

DMA AutoBahn (CS3)

Reserved, mirrored 68EN360’s CS4

Reserved, mirrored 68EN360’s CS5

Reserved, mirrored 68EN360’s CS6

Reserved, mirrored 68EN360’s CS7

Reserved (BERR_0)

MP interface (CS_AUT)

Reserved (BERR_0)

The following address area is non-cachable serialised.

VMEbus (CS_VME), user-defined AM code

VMEbus (CS_VME), short I/O AM code

VMEbus (CS_VME), user-defined AM code

DMA-VME, 68EN360’s CS2

Reserved (BERR_0)

Reserved, mirrored DRAM

Reserved, mirrored FLASH

Reserved, 68EN360 internal RAM / register

68EN360’s CS4, SRAM

68EN360’s CS5, CXC

68EN360’s CS6, RTC

68EN360’s CS7+1, VME IRQ MASK register

68EN360’s CS7+5, VME control / status register

68EN360’s CS7+7, board control / status register

Reserved (BERR_0)

Note

In order to determine the base of the 68EN360’s internal memory map, the module base address register

(MBAR) must be set. The location of this register is fixed in the address area Supervisor CPU Space at

3FF00H. For more information, please refer to the Software Configuration chapter in this manual.