Manual

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction
1.3 Specifications
Main CPU
I/O Controller
Memory
DRAM
FLASH
SRAM
EEPROM
VMEbus Interface
A24:D16/D8
Arbitration
AM Codes
A24:D16
Dual-port SRAM
1 Mailbox IRQ
Interrupt Control
7 Level VME IRQ Handler,
maskable via VME IRQ mask
register
System vectors
MC68060 66 or 50 MHz (3.3V)
MC68040 33 or 25 MHz
MC68040V 33 or 25 MHz (3.3V)
MC68LC040 33 or 25 MHz
MC68EN360, 25 or 33MHz used in companion mode
1, 4, 16 or 32 Mbyte
0.5, 1, 2, or 4 MByte
1 MByte or 256 kByte (dual-ported, backed-up using Gold-Caps)
2 kbit (serial); 1 kbit available for applications
Master and slave with optional AutoBahn Interface (100 MBytes/sec)
Single level (BR3*), release-when-done daisy-chain
Standard Superv./User Prog./Data HEX 39/3A/3D/3E
User Defined HEX 10-17/18-1F
Short I/O HEX 29/2D
System controller functions
Automatic First Slot Detection (FSD)
SYSRES* (disabled by jumper)
SYSCLK* (disabled by jumper)
ACFAIL*
SYSFAIL*
Power monitor
Bus monitor (programmable)
VME IRQ mask register
Slave
1 Mbyte window, software programmable base (1 out of 16 addresses)
Lower 8kBytes of the SRAM area
ACFAIL* -> Level 7 autovectored
ABORT -> Level 7 autovectored
TICK -> Level 6 autovectored
SYSFAIL* -> Level 3 autovectored (maskable)
*
Mailbox IRQ -> Level 5 autovectored
AutoBahn IRQ 2 -> Level 2 autovectored
AutoBahn IRQ 1 -> Level 1 autovectored
16 on-board Interrupters, Levels / Vectors programmable
* Available for Index 02 boards or later.
May 17, 1996 © 1995 PEP Modular Computers Page 1-5