VM162/VM172 VMEbus Single-Board Computer with Dual IndustryPack Support Manual Order Nr.
Table Of Contents Chapter VM162/VM172 1 Introduction ......................................................................... 1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Product Overview ......................................................................... 1-3 IndustryPack Flexibility................................................................ 1-3 Controller eXtension Connector................................................... 1-4 Front Panel and I/O Configuration ................................
Table of Contents VM162/VM172 2.6.3 2.6.4 2.6.5 2.7 Bus Timer.................................................................................................... 2-16 Watchdog Timer ......................................................................................... 2-16 Board Control/Status Register.................................................................... 2-16 Special Functions........................................................................ 2-18 2.7.1 2.7.2 2.7.3 2.7.4 2.7.
Table Of Contents 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 VM162/VM172 CPU (Bus) Clock .......................................................................................... 3-8 SRAM Size..................................................................................................... 3-8 Communications Clock................................................................................. 3-9 EEPROM Write Protection ..........................................................................
Table of Contents VM162/VM172 Page TOC- 4 © PEP Modular Computers Juli 23, 1997
VM162/VM172 Preface Juli 23, 1997 © PEP Modular Computers Page 0- 1
VM162/VM172 Preface Unpacking and Special Handling Instructions This PEP product is carefully designed for a long and fault-free life; nonetheless, its life expectancy can be drastically reduced by improper treatment during unpacking and installation. Observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings etc.
Preface VM162/VM172 Revision History Issue 1 Brief Description of Changes First Issue Index Date of Issue 0 July, 1997 This document contains proprietary information of PEP Modular Computers. It may not be copied or transmitted by any means, passed to others, or stored in any retrieval system or media, without the prior consent of PEP Modular Computers or its authorized agents. The information in this document is, to the best of our knowledge, entirely correct.
VM162/VM172 Preface PEP Modular Computers Two Year Limited Warranty We grant the original purchaser of PEP products the following hardware warranty. No other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the expressed written consent of PEP Modular Computers. PEP Modular Computers warrants their own products (excluding software) to be free from defects in workmanship and materials for a period of 24 consecutive months from the date of purchase.
VM162/VM172 Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Juli 23, 1997 Product Overview.......................................................................... 1-3 IndustryPack Flexibility ................................................................1-3 Controller eXtension Connector ................................................... 1-4 Front Panel and I/O Configuration ..............................................1-4 Features.......................................................
VM162/VM172 Page 1- 2 Chapter 1 Introduction © PEP Modular Computers Juli 23, 1997
Chapter 1 Introduction VM162/VM172 1.1 Product Overview PEP’s VM162/172 combines high computational performance and flexible I/O requirements through its twin IndustryPack and single CXC interface with excellent communication ability afforded by the Motorola ‘QUICC’ controller.
VM162/VM172 Chapter 1 Introduction 1.3 Controller eXtension Connector Although the VM162/172 adds a new dimension to computer architecture with its direct IndustryPack interface, it is also a continuation of the successful range of PEP’s CPU boards with communication processors and CXC capability. The CXC extends the already abundant industrial I/O capability of the CPU and also allows custom design according to the guidelines laid-down in the CXC specification.
Chapter 1 Introduction VM162/VM172 SC and SI6 piggybacks adapt the multi-protocol serial channels of the ‘QUICC’ to the physical interfaces provided on the VM162/172’s front-panel and CXC: SCC1 channel supports: SI6-10B5 Ethernet 10base5 (AUI) SI6-10B2 Ethernet 10base2 (Thin) SI6-10BT Ethernet 10baseT (Twisted Pair) SI6-PB485-ISO Optoisolated RS485 SCC2 to SCC4 channels support: SC-232I Optoisolated RS232 Modem module SC-485I Optoisolated RS485 piggyback U W H U W H ETHERNET 10Base5 RS485-I
VM162/VM172 Chapter 1 Introduction 1.5 Features CPU Options The 68060 processor operating at 50 Mhz provides the highest performance while the 68040(V) at 33 MHz sets the standard in the Motorola CISC portfolio. 68EN360 The ‘QUICC’ chip operates as an I/O and communication companion providing 4, high-speed serial channels, timers, clocks and Time Slot Assignment (TSA). Serial Channels All high-speed SCC channels are equipped with hardware hand-shaking and are available for a variety of applications.
Chapter 1 Introduction VM162/VM172 IndustryPack Any two IndustryPacks from a wide-range may be fitted to cater for the needs of digital, analog, communication or counter functions. PEP also offers customers a non-gratis service that integrates the chosen IP module and RT-OS with the VM162/172 carrier board. SC-Interface Three RS232 SC-Piggybacks are fitted as standard for serial communication.These can be replaced by optoisolated RS232 or RS485 piggybacks as required.
VM162/VM172 Chapter 1 Introduction 1.6 Specifications Page 1- 8 CPUs MC68040(V) @ 33 MHz MC68060 @ 50 MHz Comms. Controller MC68EN360 Companion processor for network support on SI6 piggybacks Memory 1/4/16/32 MByte (32-bit access) DRAM 0.
Chapter 1 Introduction VM162/VM172 VMEbus Interface DIN 41612 (C), 96-pin P1/P2 connector A32/A24/A16:D32/D16/D8 master A24:D16 slave Networking All Ethernet interfaces conform to IEEE 802-3 and are available on SI6-xx piggybacks SC-Interface Serial Interface from MC68EN360 (ports SCC2, SCC3 and SCC4) with standard RS232 configuration Power Consumptiona VM162 w/ MC68060 VM172 w/ MC68040 Temperature 0ºC to +70ºC (standard) -40ºC to +85ºC (extended / storage) Humidity 0 to 95% non-condensing Wei
VM162/VM172 Chapter 1 Introduction 1.7 Ordering Information Product Description Order Nr. VM172-BASE VMEbus single-board computer comprising MC68060 @ 50MHz, MC68EN360 @ 25 MHz,256 kByte dual-ported SRAM (with Goldcap for back-up), five serial interfaces (four available on the front panel as RS232 (RJ45) and one available from the choice of SI6-networking piggybacks), CXC interface, two IP interfaces and PEPbug 16134 VM172-BASE Same as order no.
Chapter 1 Introduction Product VM162/VM172 Description SI6-10BT-IP SI6DUMMY-IP 10BaseT Twisted pair Ethernet interface piggyback with RJ45 connector Front panel without networking interface(s) Order Nr. 16147 16028 SI6-PB485-IP Optoisolated RS485 interface piggyback with 9-Pin D-Sub connector 16192 SC-2321 Optoisolated RS232 interface piggyback with TxD, RxD, DTR and CTS signals and Baud rate up to 38.
VM162/VM172 Chapter 1 Introduction 1.
VM162/VM172 Chapter 2 Functional Description 2.1 2.2 2.3 VM162/VM172 Block Diagram..................................................... 2-3 CPU Options ................................................................................. 2-4 Memory..........................................................................................2-4 2.3.1 2.3.2 2.3.3 2.3.4 2.4 Communication Controller 68EN360 (QUICC) ...........................2-6 2.4.1 2.4.2 2.4.3 2.4.4 2.5 Real Time Clock ....................
VM162/VM172 2.8.3 Chapter 2 Functional Description TERM Pinouts............................................................................................. 2-23 2.9 CXC Interface ............................................................................. 2-24 2.10 IndustryPack (IP) Interface ...................................................... 2-30 2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7 2.10.8 2.10.9 2.10.10 2.10.11 2.10.12 Page 2- 2 Overview ............................................
Juli 23, 1997 0-4 MB 1-64 MB © PEP Modular Computers RESET/ ABORT Buttons LED Port Watchdog Timer Bus Timer IRQ Handler BoardControlLogic Board Register BootROM (opt.) FLASH DRAM Memory-PB IP - I/O DSUB-50 Conn. DSUB-50 Conn. FlatCable Conn. IP - I/O IP - I/O FlatCable Conn. IP Slot B IP - I/O IP Slot A IP Slots Industry Pack Interface 33 MHz 50/66 MHz A32/D32 A24/D16 FrontPanel RJ45 or MDSUB-9 RJ45 or MDSUB-9 Ser I/O (SER2) RS232 RS485 (opt.Iso) RS232 RS485 (opt.
VM162/VM172 Chapter 2 Functional Description 2.2 CPU Options By supporting several types of CPUs the VM162/VM172 provides scalable computing power at optimized costs. The CPU types differ in performance, power requirement and supported functions. Optional on-chip functions are Memory Management Unit (MMU) and Floating Point Unit (FPU). There are three categories of VM162/VM172 CPU boards. At the top there is the 68060 CPU board which offers 2 to 3 times performance of a the following 68040 CPU board.
Chapter 2 Functional Description VM162/VM172 Table 2.2: DRAM/FLASH Options Name DRAM Size FLASH Size DM600 4 MByte 1 or 4 MByte DM601 16 MByte 1 or 4 MByte DM602 1 MByte 0 or 0.5 or 2 MByte DM603 32 MByte 1 or 4 MByte DM604 8 MBytes 1 or 4 MBytes Note: DRAM is accessed with a 5-2-2-2 burst cycle at 25 MHz bus clock (68060/50MHz) and with a 62-2-2 burst cycle at 33 MHz bus clock (68040(V)/33MHz). 2.3.
VM162/VM172 Chapter 2 Functional Description 2.3.4 EEPROM The EEPROM is a non-volatile serial memory device. It provides 2 kbit size and is accessed over the SPI (Serial Peripheral Interface) of the 68EN360. 1 kbit of this EEPROM memory is free for application relevant data whereas the rest of this EEPROM is reserved. This part is used for storing board ID codes, Internet/Ethernet addresses and boot information. Note: For more information on the EPROM type, please refer to the XICOR X25C02 data sheet.
Chapter 2 Functional Description VM162/VM172 2.4.2 Use of 68EN360 Memory Controller Beside its main purpose which is to provide communication power to the VM162/VM172 the I/O controller 68EN360 is also used for some system integration function. First of all this is DRAM control and global memory decoding. Therefore, the 8 CS lines provided by the 68EN360 memory controller are connected to the different memory types or address areas folllowing the scheme in the following Table. Table 2.
VM162/VM172 Chapter 2 Functional Description Note: In order to be compatible with the above configuration, the board initialization described in the Programming Chapter must be closely adhered to. VME ACFAIL* generates a non-maskable autovector level 7 interrupt (NMI) in the same way as the ABORT button. When an ACFAIL* NMI is detected, it can be differentiated from an ABORT by reading bit 1 of the Board Configuration Register. 2.4.
Chapter 2 Functional Description VM162/VM172 2.5.1 VME Master Interface 2.5.1.1 Supported Data Transfer Types (VMEbus AM Codes) The VM162/VM172 supports three addressing modes which are A32, A24 and A16. The following AM codes according to the standard for VME64 are supported by the VM162/VM172. Table 2.
VM162/VM172 Chapter 2 Functional Description 2.5.1.2 VME Address Map The various combinations of addressing modes and data bus sizes are selected on different address areas within the address map of the CPU. The corresponding AM codes are generated according to the Table below. Table 2.
Chapter 2 Functional Description VM162/VM172 2.5.2.3 SYSRES* Generator The VM162/VM172 contains a power monitor which generates on-board system reset signal after the on-board voltage falls below 4.65 V. This on-board system reset can also drive VME SYSRES*. If the VM162/VM172 is not intended to drive VME SYSRES*, the signal can be disconnected using a jumper. Note: In contrast to SYSCLK*, which may be driven by one board in the system, SYSRES* may be driven more than once in a system.
VM162/VM172 Chapter 2 Functional Description 2.5.4 VME Address Map from the VME Side The Table below shows the VME board address map for external Master access dependent on the setting of the board address bits within the VME Control/Status Register. Table 2.7: VME Address Map Board Address Bits BADR[3-0] Board VME Base Address (HEX) Mailbox Interrupt Reg.
Chapter 2 Functional Description VM162/VM172 2.5.5 VME Control/Status Register The VME Control/Status Register is a one byte wide register with read/write access at default address CD 00 00 05 (HEX). 7 P_IRQ5 CS7 + $5 6 5 4 EN_DPR EN_BERR2 3 FSD BADR3 2 BADR2 1 0 BADR1 BADR0 Note: All bits except bit 4 (First Slot Detection) are cleared after reset. The firmware of the board initializes some of them at startup according to the default parameters stored in the EEPROM.
VM162/VM172 Chapter 2 Functional Description 2.6 Board Control Logic 2.6.1 Boot Decoder Logic The VM162/VM172 gives the user the choice to execute startup procedures from three different memory areas. These are FLASH (default on the memory Piggyback), or the optional Boot ROM or memory on the VMEbus. The boot device/memory is selected by jumpers. The boot decoder logic redirects the initial CPU access which is always starting at address 0 (HEX) to the boot device according the boot jumper setting.
Chapter 2 Functional Description VM162/VM172 2.6.2.2 External Autovectored Interrupt Requests Autovectored interrupts are all generated via the 68EN360 pins for external interrupt sources. They are summarized in the table below. Care must be taken that the relevant 68EN360 register is initialised with respect to the wiring (see also the Programming chapter in this manual). Table 2.
VM162/VM172 Chapter 2 Functional Description 2.6.3 Bus Timer The VM162/VM172 provides an 128µs timeout timer which monitors the cycle lengths of on-board data transfers, including on-board I/O, CXC, IndustryPack, dual-ported SRAM and some VME. After a timeout occurs, it generates an on-board BERR signal for error termination.
Chapter 2 Functional Description VM162/VM172 Register Description Name Juli 23, 1997 Value Access Description WDG bit 7 Read/Write Set by watchdog timer when timeout has been reached. Used to differentiate between resets caused by the watchdog and resets caused by the reset button (power up resets can be identified within the 68EN360). BERR2 bit 6 Read/Write Set by VMEbus BUS monitor when timeout has been reached.
VM162/VM172 Chapter 2 Functional Description 2.7 Special Functions 2.7.1 Real Time Clock The RTC (V3021 3-wire serial interface) is a 1-bit device which is accessible over the CS6 of the 68EN360. Its timekeeping features include: • • • seconds, minutes, hours, day of month, month, year, week day and week number in BCD format. leap year and week number correction. standby supply smaller than 1µA. For more details, please refer to the Programming Chapter in this manual and the V3021 data sheet. 2.7.
Chapter 2 Functional Description VM162/VM172 2.7.6 Data Retention for RTC and SRAM Short term data retention for RTC and SRAM is gained with two Gold-Caps, each with a value of 0.22 Farad. In contrast to Lithium cells, Gold-Caps do not require servicing. This short term backup is intended for short power failures or for reconfiguring systems. An empty Gold-Cap needs approximately three hours to charge up, with backup times dependant on the temperature, memory size and memory manufacturer tolerances.
VM162/VM172 Chapter 2 Functional Description 2.8 Serial Communication Ports The 5 serial ports of the VM162/VM172 are based on the 4 SCCs and 1 SMCs of the 68EN360. These multiprotocol serial ports can be physically translated to the different standards due to application specific demands. A view of the range of front panels available for the VM162/VM172 can be found in Figure 1.1 of this manual. Figure 2.
Chapter 2 Functional Description VM162/VM172 Table 2.9: Serial Communication Port Configuration Port Name on Front Panel 68EN360 Resource Dedicated Function Configured via SCC1 Ethernet/Fieldbus SI6-PB 10Base2 10Base5 10BaseT Isol.
VM162/VM172 Chapter 2 Functional Description 2.8.2 SER1, SER2 and SER3 Ports The three serial ports, based on the SCC2, SCC3 and SCC4 lines of the 68EN360, are configured by default as RS232 ports. They support full modem handshake and can be re-configured by other piggybacks in the SC product line. These ports are usually used for communication between systems or to subsystems/modems. In addition, the signals of SCC2, SCC3 and SCC4 are routed to the CXC.
Chapter 2 Functional Description VM162/VM172 2.8.3 TERM Pinout The port based on the SMC is fixed to RS232 interfaces. This port supply RxD/TxD interfaces with software handshake (XON/XOFF) capability. Usually, this port is used as terminal/debug port.
VM162/VM172 Chapter 2 Functional Description 2.9 CXC Interface The Controller Extension Connector (CXC) is a local mezzanine interface. The CXC contains a 16-bit data bus, 7 address lines and 8 decoded chip select lines. In total, there are 8 control signals. The base address of the CXC can be programmed via the CS5 line of the 68EN360. The 8 CXC chip selects (CXC_CS0 - CXC_CS7) occupy 256 Bytes each and have an address length of 400H (512 Bytes).
Chapter 2 Functional Description Juli 23, 1997 VM162/VM172 CXC Function Pin Nr. 68302 HW Compatible 68(EN)360 Port IRQ_1 a1 Yes PC0 IRQ_2 a2 Yes PC1 IRQ_3 a3 Yes PC2 IRQ_4 a4 Yes PC3 CXC Function Pin Nr. 68302 HW Compatible 68(EN)360 Port DMA_ACK c2 Yes PB5 DMA_REQ c3 Yes PB4 CXC Function Pin Nr.
VM162/VM172 Chapter 2 Functional Description CXC Function Pin Nr. 68302 HW Compatible 68(EN)360 Port SER2_RCLK c16 Yes PA13 SER2_TCLK c15 Yes PA12 SER2_TXD c17 Yes PA5 SER2_RXD c18 Yes PA4 SER2_RTS c12 Yes PB14 SER2_DTR a11 Yes PB16 SER2_CTS c13 Yes PC8 SER2_CD c11 Yes PC9 Comment Cannot be used if J6 is set See note 3 CXC Function Pin Nr.
Chapter 2 Functional Description VM162/VM172 CXC Function Pin Nr. 68302 HW Compatible 68(EN)360 Port user defined a5 No PB0 Used on board SPI SEL for EEPROM.
VM162/VM172 Chapter 2 Functional Description The CXC ports SER1, SER2 and SER3 are equivalent to ports SCC2, SCC3 and SCC4 resp. on the 68xx360. With regard to special CXC capabilities, the CXC pinout on the VM162/VM172 has been developed to provide maximum compatibility between the standard CXC functions. In addition, all signals are available in order to configure 2 time division multiplexed channels via the CXC (ISDN, PCM, GCI and so on).
Chapter 2 Functional Description VM162/VM172 Table 2.
VM162/VM172 Chapter 2 Functional Description 2.10 IndustryPack (IP) Interface 2.10.1 Overview The VM162/177 interface up to two IndustryPacks (IPs, referred as IPa and IPb). The implementation of the IP interfaces is according to the VITA-4 standard for IP modules. The VM162/177 (referred also as “IP-Carrier“ in this chapter) interfaces the two IP slots through a programmable IP controller. Through this controller a lot of operating functions can be controlled individually per slot.
Chapter 2 Functional Description VM162/VM172 2.10.4 IP Interface Controller The IP interface controller builts the bridge between the local CPU and the IP bus. Therefore, it synchronizes IP bus cycles with CPU cycles and performs the corresponding bus protocols. Besides, the IP interface controller provides a set of two control registers. Each set is dedicated to one IP slot. With these control registers reset, interrupt control, bus speed and memory space can be controlled individually for each IP slot.
VM162/VM172 Chapter 2 Functional Description 2.10.8 IP Memory Size Control After a board reset the IP Memory Size is set to 8 MB linear address space by default. By setting Bit 3 of the IP Slot Control register (Memory size bit) the linear addressable memory space can be reduced from 8 MB to 1 MB. If 1 MB is selected the whole IP memory address space of 8 MB is available further on.
Chapter 2 Functional Description VM162/VM172 2.10.
VM162/VM172 Chapter 2 Functional Description 2.10.
Chapter 2 Functional Description VM162/VM172 2.10.12 IP Connectors IPb I/O DSUB IPa I/O DSUB IPb I/O Flat Cable Conn. IPa I/O Flat Cable Conn. IPb I/O Conn. IPa I/O Conn. IPb IPa IPb bus IPa bus VME P2 VME P1 VME Connector VME Connector The figure above shows the position of IPa and IPb on the VM162/177. Each IP is plugged into the board via a pair of 50-pin IP connectors.
VM162/VM172 Chapter 2 Functional Description 2.10.12.
Chapter 2 Functional Description VM162/VM172 2.10.12.
VM162/VM172 Chapter 2 Functional Description This page has been intentionally left blank Page 2- 38 © PEP Modular Computers Juli 23, 1997
Chapter 3 Configuration VM162/VM172 Chapter 3 Configuration 3.1 Default Jumper Settings ................................................................ 3-3 3.1.1 3.1.2 3.2 Jumper Description (Component Side) ......................................... 3-4 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.3 VME Boot ......................................................................................................3-5 ROM Boot.........................................................................................
VM162/VM172 Page 3- 2 Chapter 3 Configuration © PEP Modular Computers Juli 23, 1997
Chapter 3 Configuration VM162/VM172 3.1 Default Jumper Settings The VM162/VM172 has four wire jumpers which can be configured by the user. Additionally, the VM162/VM172 has a set of solder jumpers which are factory set. The list of default settings are shown below. 3.1.
VM162/VM172 Chapter 3 Configuration 3.2 Jumper Description (Component Side) J1 VME Boot J2 ROM Boot J11 CXC Mode VME SYSRES * J10 VME VME Connector P1 Connector J8 Protective GND Signal GND VME VME Connector P2 Connector RJ45/Mini-D-Sub Serial port Connectors RJ45, RJ58 or 15-Pin D-Sub Connector Figure 3.
Chapter 3 Configuration VM162/VM172 3.2.1 VME Boot The VM162/VM172 normally boots from the FLASH memory on the DM60x piggyback. In some applications it may be useful to boot either from the VMEbus or the optionally assembled EPROM. Jumper Setting Description J1 Open Boot from VMEbus enabled Set Boot from VMEbus disabled Jumper Setting Description J2 Set Boot from boot ROM enabled Open Boot from boot ROM disabled Default 3.2.2 ROM Boot Default 3.2.
VM162/VM172 Chapter 3 Configuration 3.2.5 CXC Mode The enhanced CXC describes the multiplexing of the CXC address lines in order to enhance the address range to 16MByte. This is used today in conjunction with the CXM-PFB12 PROFIBUS board. Please consult the relevant CXM User’s Manual to set the CXC mode.
Juli 23, 1997 © PEP Modular Computers J18 J21 J12 J13 J14 J15 J3 J4 J5 J6 RJ45/Mini-D-Sub sSerial port Connector VME Connector P1 rotcennoC EMV J17 RJ45, RJ58 or 15-Pin D-Sub Connector J22 J9 J20 J16 J19 rotcennoC EMV VME Connector P2 Chapter 3 Configuration VM162/VM172 3.3 Jumper Description (Solder Side) Figure 3.
VM162/VM172 Chapter 3 Configuration 3.3.1 CPU Type Jumper Setting Description J3 Set CPU type is 68060 Open CPU type is 68040 or 68040V 3.3.2 CPU Power Supply Jumper Setting Description J12 - J15 1-2 CPU power is 5 volt (68040) 1-3 CPU power is 3.3 volt (68040V or 68060) 3.3.3 CPU (Bus) Clock Jumper J5 - J7 Setting Description J5 J6 Set Set CPU Bus clock is 25.0 MHz Open Set CPU Bus clock is 33.3 MHz 3.3.
Chapter 3 Configuration VM162/VM172 Note: The above solder jumpers describe the basic configuration of the board. They are factory set and should not be altered by the user. Alteration of these jumpers can result in damage to the board. 3.3.5 Communications Clock Jumper Setting Description J4 Set 24 MHz connected to 68EN360 RCLK2 pin Open 24 MHz disconnected from 68EN360 RCLK2 pin Default 3.3.
VM162/VM172 Chapter 3 Configuration 3.3.8 SRAM Data Retention The battery backup of the VM162/VM172 is connected to both the SRAM and RTC. This jumper gives the user the possibility to disconnect the SRAM from the battery backup, giving the RTC longer backup support. Jumper Setting Description J16 1-2 SRAM data retention is off 1-3 SRAM data retention is on Default 3.3.9 BERR1 Timeout This jumper sets the timeout of the BERR1 and can be used for debugging purposes.
Chapter 4 Programming VM162/VM172 Programming 4.1 4.2 4.3 July 19,1997 VM162/VM172 Address Map ........................................................ 4-3 Initializing the 68EN360 ............................................................... 4-4 Initializing the Cache ....................................................................
VM162/VM172 Page 4- 2 Chapter 4 Programming © PEP Modular Computers July 19, 1997
Chapter 4 Programming VM162/VM172 4.1 VM162/VM172 Address Map Address range less than HEX 80 00 00 00 is to be initialized as cachable address areas and address range greater than HEX 80 00 00 00 is to be initialized as non-cachable serialized address area. Base Address (HEX) Size Device Description 00 00 00 00 04 00 00 00 max. 64 MB max. 64 MB DRAM FLASH 68360 CS1, DRAM on DM60x, 32 bit 68360 CS0, FLASH on DM60x, 32 bit 07 00 00 00 0A 00 00 00 0B F7 00 00 0C 00 00 00 0D 00 00 00 4 KB max.
VM162/VM172 Chapter 4 Programming 4.2 Initializing the 68EN360 Many components of the VM62(A) / VM42(A) are controlled by the MC68EN360. Due to this fact, this chip requires a special initialization sequence before any other software can be started. The following list describes how the initialization must be performed on the VM62(A) / VM42(A). Note: The order of the initialization listed below must not be changed, otherwise erratic behaviour of the board may result.
Chapter 4 Programming VM162/VM172 8) Configure PEPAR register • set /IOUT0-2 are PRTY0-2 • select /RAS1DD function • select /WE0-3 • select AMUX • select /CAS0-3 0x51C0.W -> PEPAR 9) Configure GMR register • set refresh counter period to 24 • set refresh cycle length to 3 • set DRAM port size to 32 bit • assert CS/RAS on CPU space • enable refresh 0x18800100.L -> GMR 10)Configure autovector register • enable autovector on levels 2, 3, 5 and 7 0xAC.
VM162/VM172 Chapter 4 Programming • CS5: size to 8 kByte, port size external, tcyc 1 • CS5: CXC to 0xBF70000 0x1FFFE006.L -> OR5 0xBF70001.L -> BR5 • CS6: size to 2 kByte, port size external, tcyc 1 • CS6: RTC to 0xC000000 0x1FFFF806.L -> OR6 0xC000001.L -> BR6 • CS7: size to 16 MByte, port size external, tcyc 1 • CS7: on-board control to 0xD000000 0x1F000006.L -> OR7 0xD000001.
Chapter 4 Programming VM162/VM172 Address List of Involved Registers MBAR 0x3FF00 RSR SYPCR MCR PLLCR CDVCR CLKOCR PEPAR GMR AVR BR0 OR0 BR1 OR1 BR2 OR2 BR3 OR3 BR4 OR4 BR5 OR5 BR6 OR6 BR7 OR7 0xC0001009 0xC0001022 0xC0001000 0xC0001010 0xC0001014 0xC000100C 0xC0001016 0xC0001040 0xC0001008 0xC0001050 0xC0001054 0xC0001060 0xC0001064 0xC0001070 0xC0001074 0xC0001080 0xC0001084 0xC0001090 0xC0001094 0xC00010A0 0xC00010A4 0xC00010B0 0xC00010B4 0xC00010C0 0xC00010C4 CICR SDCR 0xC0001540 0xC000151E VCSR
VM162/VM172 Chapter 4 Programming Accesses to the DRAM and FLASH should be made at $0 and $4000000. All other components addressed by the MC68EN360 should always be accessed over the mirrored area with $Cxxxxxxx, as described in the Address Map Section.
Appendix Memory Piggybacks APPENDIX MEMORY PIGGYBACKS A number of piggybacks have been developed for PEP’s range of CPU boards to enhance their memory capabilities. • DM600 piggyback with 4 MByte DRAM and 1 or 4 MByte FLASH; • DM601piggyback with 16 MByte DRAM and 1 or 4 MByte FLASH; • DM602 piggyback with 1 MByte DRAM and 1 MByte FLASH; • DM603 piggyback with 32 MByte DRAM and 1 or 4 MByte FLASH; • DM604 piggypack with 8 MB DRAM and 1 or 4 MByte FLASH.
Appendix Memory Piggybacks 1 DM600 The DM600 is a memory piggyback fitted with 4MByte DRAM and either 1 or 4MByte FLASH. 1.
Appendix Memory Piggybacks 2 DM601 The DM601 is a memory piggyback fitted with 16MByte DRAM and either 1 or 4MByte Flash EPROM. 2.
Appendix Memory Piggybacks 3 DM602 The DM602 is a memory piggyback fitted with 1MByte DRAM and either 0 or 1MByte Flash EPROM. 3.
Appendix Memory Piggybacks 4 DM603 The DM603 is a memory piggyback fitted with 32MByte DRAM and either 0.5MByte or 2MByte Flash EPROM. 4.
Appendix Memory Piggybacks 5 DM604 The DM604 is a memory piggyback fitted with 8MByte DRAM and either 1 or 4MByte Flash EPROM. 5.
Appendix SI6 Piggybacks APPENDIX SI6 PIGGYBACKS A number of piggybacks have been developed for PEP’s range of 6U CPU boards to adapt the multi-protocol serial channels of the 68EN360 controller chip to one of the following physical interfaces: • Ethernet 10Base2 (Thin) with SI6-10B2 piggyback; • Ethernet 10Base5 (AUI) with SI6-10B5 piggyback; • Ethernet 10BaseT (Twisted Pair) with SI6-10BT piggyback; • RS485 optoisolated (PROFIBUS) with SI6-PB485-ISO piggyback.
Appendix SI6 Piggybacks 1 SI6-10B2 The SI6-10B2 is a physical Cheapernet (10Base2) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to a 50Ω coax cable via an RG58 BNC ‘T’ connector. The SI6-10B2 has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data. 1.1 Specifications On-board termination None (Cheapernet cable is terminated at both ends) Max. Baud Rate 10 Mbit/s as specified by Ethernet 1.
Appendix SI6 Piggybacks 2 SI6-10B5 The SI6-10B5 is a physical AUI Ethernet interface to the 68EN360 Controller chip. 2.1 Specifications On-board termination None (Cheapernet cable is terminated at both ends) Max. Baud Rate 10 Mbit/s as specified by Ethernet Connector Pin 1 Pin 2 Pin No. Signal ETHERNET 10Base5 2.2 4 Pin 9 15-pin D-Sub Connector Pin 15 Pin No.
Appendix SI6 Piggybacks 3 SI6-10BT The SI6-10BT is a physical twisted pair (10BaseT) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to an unshielded 100Ω twisted pair cable via an RJ45 telephone jack. The SI6-10BT has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data. 3.1 Specifications On-board termination 100Ω Max. Baud Rate 10 Mbit/s as specified by Ethernet 3.2 Connector Data Collision Col Tx Pin 8 Pin 1 Pin No.
Appendix SI6 Piggybacks 3.3 Jumper Location 4 J3 J2 J1 Jumper J1: Squelch Threshold Setting Descirption Open Normal Set 4.
Appendix SI6 Piggybacks 4 SI6-PB485-ISO The SI6-10BT is an RS485 optoisolated interface piggyback for 2-wire half-duplex (PROFIBUS) connection. It has one LED fitted indicating data transmission. 4.1 Specifications On-board termination 150Ω, jumper selectable Isolation Voltage Optocoupler specified up to 2.5 kV Max. Baud Rate 10 Mbit/s as specified by Ethernet 4.2 Connector Pin No. Signal Description 1 SHIELD Shield, Protective Ground resp.
Appendix SI6 Piggybacks 4.
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Appendix Bootstrap Loader APPENDIX BOOTSTRAP LOADER FOR VM(6)62, VM(6)42, VSBC 32 AND IUC-32 1 Introduction 4 The Bootstrap Loader is a stand alone software located in FLASH memory which allows the user to safely update the contents of the FLASH and delay the boot process for a specified time. The Bootstrap Loader has the capability of programming FLASH memory from MOTOROLA S-records or from an absolute address. If the programmed image does not work, the Bootstrap Loader can be entered again.
Appendix Bootstrap Loader 2 System Operation 2.1 Startup After system reset, the Bootstrap Loader is started. It searches the FLASH memory area for a valid start key. If this start key is found, the Bootstrap Loader checks the 'BootWaitTime' from serial EEPROM. If the time is valid, the continuation of the boot process is delayed by this time while flashing the green front panel LED to indicate that the system is alive but waiting for continuation.
Appendix Bootstrap Loader 3 Programming FLASH Memory 3.1 Preparing the Image 4 The image must be compiled / linked to run from the FLASH base address 0x4000000. The image must start with the ResetSP / ResetPC vectors as usual for ROM / FLASH images on 68000 processor boards. A binary image must be converted to Motorola S-records or loaded to a VME memory board with battery-backup, FLASH or EPROM population. 3.2 Programming with Motorola S-Records Programming is done with the If command.
Appendix Bootstrap Loader Example 1: The host is assumed to be an OS-9 development system. A serial cable is used to connect the ser0 port of the board to program to t0 of the development system. Additionally, we assume that we want to program a PEPbug image which is available as a file 'pbVM42' in a binary image format. The serial connection should run at 38400 Baud.
Appendix Bootstrap Loader None of the above characters indicate an error. The first sector (which includes Reset SP / PC) and the last sector (which includes the Bootstrap Loader itself) are protected. These sectors are not immediately programmed like the other sectors. The contents of these protected sectors are buffered in RAM and programmed at the end of the operation.
Appendix Bootstrap Loader 3.4 Boot Wait Time The command bw can be used to display / change the current BootWaitTime. Available delays are 1-2-5-10-20-50 seconds. Note: The BootWaitTime is stored in the boot section of the serial EEPROM. This section is validated with a CRC code to avoid the setting of random parameters.
Appendix Bootstrap Loader 4 Command Reference 4.1 Boot Wait Syntax bw [
Appendix Bootstrap Loader 4.3 Memory Display Syntax md [] Description Without parameters specified, the FLASH contents starting at 0x4000000 are displayed. This function is not limited to FLASH and other address ranges can be specified. Note: The ResetPC in FLASH is not identical to the ResetPC from the programming source (S-records memory block). 4.
Set the stopbits field to 2 for ser0: pf ser0 ///2 4.5 Reset System Syntax rs Description This command exits the Bootstrap Loader and resets the system. It terminates the Bootstrap Loader command mode and resets the complete system, generating a system reset with the on-board watchdog. 4.
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Appendix CXC Controller eXtension Connector APPENDIX CXC. CONTROLLER EXTENSION CONNECTOR 4 The Controller eXtension Connector (CXC) is the local interface. It contains a 16-bit data bus, 7 address lines and 8 decoded chip select lines. Each select line has 256 bytes. In total, there are 8 select signals.
Appendix CXC Controller eXtension Connector 2 CXC Generic Pinouts Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Page CXC- 2 Row A Signals IRQ_1 IRQ_2 IRQ_3 IRQ_4 user defined user defined Vcc user defined user defined user defined SER2_DTR SER3_DTR SER1_DTR Vcc _CS-CXC _AS R/_W _UDS _LDS Vcc A1 A2 A3 A4 A5 Vcc D0 D1 D2 D3 D4 D5 Row B Signals SER1_RCLK SER1_TCLK GND SER1_TXD SER1_RTS GND SER3_RTS SER3_CD GND SER1_RXD user defined GND SER1_CTS SER1_
Appendix CXC Controller eXtension Connector 3 CPU Pinout Cross Reference The table below shows a cross reference of the special CXC released by the 68302 and the 68EN360. 4 Table 3.0.
Appendix CXC Controller eXtension Connector 4 Timing KEY 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
Appendix CXC Controller eXtension Connector 5 Controller Extension Connectors 4 When using an 8TE board on the CXC5 and CXC8 note that a slot will be lost between each board.
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Appendix OS-9 Cabling APPENDIX OS-9 CABLING This Appendix outlines the connection definitions of =S-9 systems to various outside media. 1 OS-9 System <-> Terminal 1.1 Software (XON/XOFF) or no Handshake 4 1.1.1 15-pin Connector on OS-9 Side 1.1.
Appendix OS-9 Cabling 1.1.
Appendix OS-9 Cabling 1.2 Hardware Handshake (Set Terminal to CTS/DTR Handshake) 4 1.2.1 15-pin Connector on OS-9 Side 1.2.
Appendix OS-9 Cabling 2 OS-9 System <-> PC 2.1 Software (XON/XOFF) or no Handshake 2.1.1 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side 2.1.
Appendix OS-9 Cabling 2.1.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-pin Connector on PC Side 4 2.1.
Appendix OS-9 Cabling 2.1.5 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 9-pin Connector on PC Side 2.1.
2.2 Hardware Handshake (Select RTS/CTS Handshake on the PC Side) 2.2.1 15-pin Connector on OS-9 Side, 25-pin Connector on PC Side 2.2.
Appendix OS-9 Cabling 2.2.3 8-pin RJ45 Connector on OS-9 Side (SMART I/O), 25-pin Connector on PC Side 2.2.
3 OS-9 System <-> Modem 3.1 15-pin Connector 3.
Appendix OS-9 Cabling 4 OS-9 System <-> OS-9 System 4.1 Software (XON/XOFF) or no Handshake 4.1.1 15-pin Connector 4.1.2 8-pin RJ45 Connector (SMART I/O) 4.1.
4.2 Hardware Handshake 4.2.1 15-pin Connector 4.2.
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