Owner manual

Kontron Modular Computers GmbH ID 31440, Rev. 01
P R E L I M I N A R Y
RevNr. = CP384 - 31440_01 - 060503/144233
Page 5 - 4
System Considerations CP384
5.5 Process-Side Signal Conditioning for Digital Inputs
Input signals presented to the CP384 must be within the ranges specified for signals in table 1-
4 or erroneous results will occur as well as possible damage to the CP384.
5.6 External Power Supply for Digital Outputs
Voltage sources presented to the CP384 must be within the ranges specified in table 1-5 or
erroneous results will occur as well as possible damage to the CP384.
In addition to the external supply of the input voltage for the relay logic parts which are linked
to the digital outputs, the operational voltages for the outputs must also be supplied externally.
5.7 Cable Interfacing
No modification to the CP384 itself is permitted.
If necessary, cabling to the CP384 CON2 connector should be physically fixed to prevent strain
on the CON2 connector.
Table 5-1: Debouncing Periods
CLOCK DIVIDER
INPUT SAMPLE CLOCK
@ 33 MHz PCI CLK
INPUT SAMPLE PERIOD
@ 33 MHz PCI CLK
1 (default value - see note below) 33 MHz 30 ns
2^8 128 kHz 8 µs
2^10 32 kHz 32 µs
2^12 8 kHz 128 µs
2^14 2 kHz 0.5 ms
2^16 0.5 kHz 2 ms
2^18 125 Hz 8 ms
2^20 31 Hz 32 ms
Note ...
The clock divider default value is 1. In addition to the choice of debouncing fil-
ters, there is an analog filter implemented on board with an edge frequency at
10 kHz.
Warning!
Each channel has a maximum current of 0.5 A. In situations where many chan-
nels are carrying a high current, separate, larger gauge cables for the external
power supply should be used.