Owner manual

Kontron Modular Computers GmbH ID 31440, Rev. 01
P R E L I M I N A R Y
RevNr. = CP384 - 31440_01 - 060503/144232
Page 4 - 14
Configuration CP384
4.4.9 Generating Interrupts
For digital outputs, a detected fail flag set in the register can trigger an interrupt. For digital
inputs, a detected event or in other words any event flag set in the Input Status Register can
trigger an interrupt. Thus, any input can be enabled individually for interrupt generation.
Independent of the interrupt cause, a board interrupt is handled on the hardware level always
in the same way.
After having set the input control registers where compare data and events are defined, inter-
rupts can be enabled individually within the Input IRQ Enable Register. Within the interrupt ser-
vice routine, interrupts should be handled as follows.
1. Check if the board is the cause of the interrupt (General Interrupt Pending is set).
2. If yes, check the reason for the interrupt by reading the fail flag in the output status reg-
ister and by reading the digital input status register.
3. Reset the corresponding Flag by writing a "1" to a set status bit (fail) or to the Input Event
Flag.
4. Reset the board’s IRQ by resetting the General Interrupt Pending Bit by writing a "1" to
that status bit.
5. Return from Interrupt.
Note ...
The board will continue issuing an interrupt until all interrupt sources are han-
dled completely and no interrupt condition remains.
Note ...
A set bit means that the board’s interrupt is enabled.
Table 4-17: General Interrupt Enable Register
BITS TYPE DEFAULT FUNCTION
31 r/w 0 Board Interrupt Enable
30 - 0 r/w 0 Reserved
Table 4-18: General Interrupt Pending Register
BITS TYPE DEFAULT FUNCTION
31 r/w 0 Board Interrupt Pending
29 - 0 r/w 0 Reserved
Note ...
A set bit means that the board’s interrupt is pending. A board interrupt must be
cleared by writing a "1" to the corresponding output irqen event flag.