CP384 Manual ID: 31440, Rev. Index 01 3 May 2006 RevNr.
Preface CP384 Revision History Publication Title: PUB ID: Rev. Index 31440 Brief Description of Changes Initial issue Date of Issue 3 May. 2006 Imprint Kontron Modular Computers GmbH may be contacted via the following: MAILING ADDRESS TELEPHONE AND E-MAIL Kontron Modular Computers GmbH +49 (0) 800-SALESKONTRON Sudetenstraße 7 sales@kontron.com D - 87600 Kaufbeuren Germany For further information about other Kontron Modular Computers products, please visit our Internet web site: www.kontron.
CP384 Preface Revision History .........................................................................................................ii Imprint ........................................................................................................................ii Disclaimer ..................................................................................................................ii Table of Contents ..............................................................................................
Preface CP384 Chapter 2. 2 Functional Description ..........................................................................................2 - 3 2.1 General Information .................................................................................2 - 3 2.2 Board Level Interfacing Diagram .............................................................2 - 3 2.3 Digital Input Signal Conditioning ..............................................................2 - 5 2.4 Digital Output Signal Conditioning ...
CP384 Preface 4.2.2 Signal Characteristics ..................................................................... 4 - 3 4.2.3 Channel Configuration .................................................................... 4 - 4 4.3 Digital Output Signal Properties .............................................................. 4 - 5 4.3.1 Channels ......................................................................................... 4 - 5 4.3.2 Connection of External Supply ............................
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CP384 Preface RevNr. = CP384 - 31440_01 - 060503/144225 1-2 System Relevant Information ................................................................... 1 - 7 1-3 CP384 Main Specifications .................................................................... 1 - 10 1-4 CP384 Digital Input Specifications ......................................................... 1 - 11 1-5 CP384 Digital Output Specifications ...................................................... 1 - 11 1-6 Applied Standards ....
Preface CP384 ROM Status Register .............................................................................. 4 - 16 4-25 ROM Data Register ................................................................................ 4 - 16 5-1 Debouncing Periods ................................................................................. 5 - 4 RevNr. = CP384 - 31440_01 - 060503/144225 PRELIMINARY 4-24 Page viii Kontron Modular Computers GmbH ID 31440, Rev.
CP384 Preface List of Figures 1-1 CP384 System Level Interfacing Diagram ............................................... 1 - 8 1-2 CP384 Front Panel .................................................................................. 1 - 9 1-3 CP384 Board (Front View) ....................................................................... 1 - 9 2-1 CP384 Board Level Interfacing ................................................................
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CP384 Preface Proprietary Note This document contains information proprietary to Kontron Modular Computers GmbH. It may not be copied or transmitted by any means, disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron Modular Computers GmbH or one of its authorized agents.
Preface CP384 Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Please refer also to the section “Applied Standards” in this manual. Caution, Electric Shock! This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them.
CP384 Preface For Your Safety Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements. It was also designed for a long fault-free life. However, the life expectancy of your product can be drastically reduced by improper treatment during unpacking and installation.
Preface CP384 General Instructions on Usage In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by Kontron Modular Computers GmbH and described in this manual or received from Kontron’s Technical Support as a special handling instruction, will void your warranty.
CP384 Preface Two Year Warranty Kontron Modular Computers GmbH grants the original purchaser of Kontron’s products a TWO as described in the following. However, no other warranties that may be granted or implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron Modular Computers GmbH.
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Introduction Chapter 1 RevNr. = CP384 - 31440_01 - 060503/144227 Introduction ID 31440, Rev.
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CP384 Introduction 1. Introduction 1.1 System Overview Many system relevant CompactPCI features that are specific to Kontron Modular Computers CompactPCI systems may be found described in the Kontron CompactPCI System Manual. Please refer to the section “Related Publications” at the end of this chapter for the relevant ordering information. The CompactPCI System Manual includes the following information: RevNr.
Introduction 1.2 CP384 Product Overview The CP384 Digital Input and Digital Output Controller is part of a comprehensive concept to provide CompactPCI system integrators with a complete range of CompactPCI I/O products which include the functions of analog input, analog output, digital input, and digital output implemented as separate individual boards. This concept ensures a maximum degree of system design flexibility thus allowing efficient and effective usage of available resources.
CP384 Introduction The following table provides a quick overview of the CP384 board.
Introduction 1.3.1.1 CP384 Board Introduction - Digital Input The digital input cluster consists of 16 input channels. The source of the digital inputs must be a voltage generator. The board accepts only differential voltages up to a maximum of +30V. The input current is limited to 5 mA over the specified input voltage range. Input signal processing begins with the presentation of the signal to the front panel connector.
CP384 1.3.
Introduction 1.5 CP384 Board Diagrams The following diagrams illustrate board functionality and component layout. 1.5.1 System Level Interfacing Figure 1-1: CP384 System Level Interfacing Diagram CompactPCI System System Master Digital Input and Output System CP384 CP384 n 1 digital input digital input 16 max 16 max 1 1 digital input digital input digital output digital output 8 max 8 max 1 1 digital output Page 1 - 8 RevNr.
CP384 1.5.2 Introduction Front Panel Figure 1-2: CP384 Front Panel RUN FAIL 1.5.3 A green “Run” LED and a red “Fail” LED have been placed on the front panel, to cater for the most likely use of these LEDs. However, they are user configurable and may be employed for user defined purposes. PRELIMINARY CP 384 Board Layout Figure 1-3: CP384 Board (Front View) O P T O LED1 Digital Input Signal Conditioning RevNr. = CP384 - 31440_01 - 060503/144227 C O N 2 Channels 0 ...
Introduction 1.
CP384 Introduction Table 1-4: CP384 Digital Input Specifications TYPE Input Voltage Range DESCRIPTION Low: -3V to +5V Channels 16 channels isolated from the system side. They do not share common GND or VCC. Channel Connections 2 pins per channel; differential input Input Filter (edge frequency) 10 kHz Input Protection 8 kV ESD Isolation 2 kV process to system Input Impedance Minimum: 1.
Introduction CP384 Table 1-5: CP384 Digital Output Specifications (Continued) TYPE DESCRIPTION External Supply Voltage (VCC) + 24V ± 20% (working range) External Supply Current (VCC) All relays ON: • 90 mA at 19.2V • 110 mA at 24.0V Signal Output Over Current Protection No over current protection is provided by the CP384 for the digital outputs. If over current protection is required, it must be provided by the application system.
CP384 1.8 Introduction Applied Standards The Kontron Modular Computers’ CP384 board complies with the requirements of the following standards: Applied Standards COMPLIANCE CE Mechanical Environmental and Health Aspects 1.9 TYPE STANDARD TEST LEVEL Emission EN55022 EN61000-6-3 -- Immission EN55024 EN61000-6-2 -- Electrical Safety EN60950-1 -- Mechanical Dimensions IEEE 1101.
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Functional Description Chapter 21 RevNr. = CP384 - 31440_01 - 060503/144228 Functional Description ID 31440, Rev.
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CP384 2. Functional Description Functional Description The following chapters present more detailed, board level information about the CP384 Digital Input and Digital Output Controller whereby the board components and their basic functionality are discussed in general. 2.1 General Information • • • • • • • • 2.
Functional Description CP384 Figure 2-1: CP384 Board Level Interfacing CP384 Digital Input and Digital Output Controller CPCI Interface PRELIMINARY DIO ProComm Controller Optoisolation DIGOUT CLUSTER DIGIN CLUSTER Signal Cond. Signal Cond. RELAYS Inputs 0 ... 15 Outputs 0 ... 7 Digital Output Page 2 - 4 RevNr. = CP384 - 31440_01 - 060503/144228 Reset & Supply Voltage Digital Input Kontron Modular Computers GmbH ID 31440, Rev.
CP384 2.3 Functional Description Digital Input Signal Conditioning The digital input signal conditioning consists of the following: 2.4 Overvoltage protection Low-pass signal filtering Current limitation Inverse polarity protection Input signal high-low determination Output signal stabilization buffering Digital Output Signal Conditioning The major element of the digital output signal conditioning is the 2 Form C relay which is able to switch inductive, capacitive or resistive loads.
Functional Description CP384 The connection for the external supply (+24V DC ± 20%) is realized by reserved/defined pins within the output cluster at the front panel connector CON2. Note ... The external power is supplied only to the relay coils. Within the CP384, the external supply power is galvanically isolated from all digital output pins on CON2 At power up, all digital outputs are switched off (NC).
CP384 Functional Description Table 2-1: Pinout of the Digital Input and Output Interface Connector CON2 DIGIN SIGNAL PIN SIGNAL PIN SIGNAL 42 DIN0- 21 DIN0+ 62 DIN1+ 41 DIN2+ 20 DIN1- 61 DIN2- 40 DIN3- 19 DIN3+ 60 DIN4+ 39 DIN5+ 18 DIN4- 59 DIN5- 38 DIN6- 17 DIN6+ 58 DIN7+ 37 DIN8+ 16 DIN7- 57 DIN8- 36 DIN9- 15 DIN9+ 56 DIN10+ 35 DIN11+ 14 DIN10- 55 DIN11- 34 DIN12- 13 DIN12+ 54 DIN13+ 33 DIN14+ 12 DIN13- 53 DIN14 - 32 DIN15- 11 DIN15+
Functional Description 2.7.2 CP384 CPCI Interface and Pinout The CPCI interface is based on the specification PICMG 2.0 R 3.0, 10/1/99. The following figure and table indicate the pin layout and pinout of the CPCI connector, CON1 (J1). Figure 2-3: CPCI Connector CON1 (J1) F EDCBA PRELIMINARY 25 CON1 RevNr. = CP384 - 31440_01 - 060503/144229 1 Page 2 - 8 Kontron Modular Computers GmbH ID 31440, Rev.
CP384 Functional Description Table 2-2: Pinout of the CPCI Connector CON1 (J1) PIN ROW A B C D E F 1 NC NC NC NC NC GND 2 NC NC NC TDO TDI GND 3 INTA# NC NC NC NC GND 4 NC GND NC NC NC GND 5 NC NC RST GND NC GND 6 NC GND 3.3V CLK AD[31] GND 7 AD[30] AD[29] AD[28] GND AD[27] GND 8 AD[26] GND NC AD[25] AD[24] GND 9 C/BE[3] IDSEL AD[23] GND AD[22] GND 10 AD[21] GND 3.
Functional Description 2.8 CP384 CapROM EEPROM The CapROM is a 4 kbit (512 byte) EEPROM which provides the capability to store board control relevant information to allow software configuration of the CP384. 2.9 Monitor and Control (M/C) Various monitor and control functions are available for the operation of the CP384. The front panel of the board is equipped with two LEDs for user-defined purposes.
Installation Chapter 31 RevNr. = CP384 - 31440_01 - 060503/144229 Installation ID 31440, Rev.
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CP384 3. Installation Installation The CP384 has been designed for easy installation. However, the following standard precautions, installation procedures, and general information must be observed to ensure proper installation and to preclude damage to the board or injury to personnel. 3.1 Hardware Installation The product described in this manual can be installed in any available 3U slot of a CompactPCI system except for the system master slot.
Installation 3.1.2 CP384 Installation Procedures To install the board proceed as follows: 1. Ensure that the safety requirements indicated above are observed. Warning! Failure to comply with the instruction below may cause damage to the board or result in improper system operation. Please refer to chapters 4 and 5 for configuration information. 2. Ensure that the board is properly configured for operation before installing.
CP384 3.1.3 Installation Removal Procedures To remove the board proceed as follows: 1. Ensure that the safety requirements indicated above are observed. Warning! Care must be taken when applying the procedures below to ensure that when the board is removed it is not damaged through contact with other boards in the system. 1. Unlock the insertion/extraction handle by pressing down on the grey locking mechanism in the middle of the handle. (This should be achievable with a minimum of force.
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Configuration Chapter 41 RevNr. = CP384 - 31440_01 - 060503/144230 Configuration ID 31440, Rev.
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CP384 4. Configuration Configuration This chapter provides information for configuring the CP384 board for operation. 4.1 Jumper Settings The CP384 does not have any jumpers which require configuring. 4.2 Digital Input Signal Requirements 4.2.1 Channels The CON2 connector of the CP384 provides two input pins per channel. This allows each channel to be configured separately as required.
Configuration 4.2.3 CP384 Channel Configuration The following figure illustrates the typical schematic of an input channel. Figure 4-2: Input Channel Schematic System Input Cluster to system Signal Input D JFET G Signal inputs are required to be connected: plus to plus, minus to ground as shown in figure 4-3 below. Figure 4-3: Input Configuration (Example for Channel 0) CP384 + Voltage Source DIGIN0+ Pin21 V DIGIN0Pin42 RevNr.
CP384 Configuration Figure 4-4: Configuration Diagram for All Input Channels Digital Sensors CON2 Ch 0 + V Ch 15 CP384 4.3 Digital Output Signal Properties In addition to the output signal type and its range, which have been specified in table 1-5, system integrators must be aware of certain output configuration requirements for the CP384. The following paragraphs provide some information regarding individual connection configuration requirements. 4.3.
Configuration 4.3.3 CP384 Channel Connection The following diagrams illustrate the external connection of the CP384 to the application. Figure 4-5: Digital Output Connectionr CON2 Supply Voltage NC NO + NC L O A D V Channel 0 C Channel 7 C NO ExtGND CP384 External GND Figure 4-6: Digital Output Circuit CON2 Supply Voltage External VCC Ch 0 NO External VCC + V L O A D NC NC NO relay coil C C relay driver EXTGND External GND Page 4 - 6 RevNr.
CP384 Configuration Figure 4-7: External Reset Connection External VCC + digital output channels VCC { V 0 Ch 0 7 Ch 7 R Reset EXTGND CP384 External GND Note ... The voltage source for the cluster is an external supply in the range 24V DC ± 20%, and it supplies only the power to drive the relay control circuits, but not the output channels themselves. RevNr. = CP384 - 31440_01 - 060503/144230 The channel output pins are galvanically isolated from the VCC within the CP384 board.
Configuration CP384 4.4 Programming Interface 4.4.1 Access Control Logic (Address Decoder) All the resources of the CP384 are mapped within the 64 kB PCI memory address space which itself is set in the PCI configuration register BAR0. The port size of all local or backend registers is 32-bit by default. The address map of the registers is as follows.
CP384 4.4.2 Configuration Reading Input Data The input ports are made visible via the Input Data Register. This register reflects the inputs after them having passed the digital programmable debouncer. An active input appears there as a logical "1" whereas an open or inactive input port appears as a logical "0". The bit ordering naturally corresponds with the numbering of the input ports at the connector.
Configuration CP384 Note ... The inputs are sampled through the debouncer after the Input Enable bit is set. Additional features such as event and pattern detection and latch mode are also enabled in the input control register, after being configured within the corresponding mode registers. deb [2 ... 0] CLOCK DIVIDER INPUT SAMPLE CLOCK @ 33MHz PCI INPUT SAMPLE PERIOD @ 33MHz PCI 000 1 33 MHz 30 ns 001 2^8 128 KHz 8 µs 010 2^10 32 KHz 32 µs 011 2^12 8 KHz 128 µs 100 2^14 2 KHz 0.
CP384 Configuration Table 4-7: Input Event Polarity Register BITS TYPE DEFAULT FUNCTION 31-16 r/w 0 Not used 15 - 0 r/w 0 Input event polarity bits Note ... A bit setting of 0 bit means that an event is detected when the input port changes from 0 to 1 whereas a setting of 1 means that an event is detected when the input changes from 1 to 0.
Configuration 4.4.6 CP384 Comparing Input Patterns In addition to the Event Detection Mode, it is also possible to detect a complete input pattern automatically. In this mode the input vector is continuously compared with the content of the Input Pattern Compare Register. In the case of a match a flag is set within the Input Status Register. Single inputs can also be masked out individually in the Input Pattern Mask Register.
CP384 Configuration Table 4-13: Output Control Register BITS TYPE DEFAULT FUNCTION 31-2 r/w 0 Reserved 1 r/w 0 irqen 0 r/w 1 Reset Note ... irqen is for enabling of a diagnostic interrupt. The reset bit should be set to 0 to activate the cluster. BITS TYPE DEFAULT FUNCTION 31 r 0 Fail 30 r 0 Diag 29-0 r 0 Reserved Note ... The Diag status flag is the diagnostic bit from the external voltage supervisor; Fail is the latched Diag status flag. 4.4.
Configuration 4.4.9 CP384 Generating Interrupts For digital outputs, a detected fail flag set in the register can trigger an interrupt. For digital inputs, a detected event or in other words any event flag set in the Input Status Register can trigger an interrupt. Thus, any input can be enabled individually for interrupt generation. Independent of the interrupt cause, a board interrupt is handled on the hardware level always in the same way. 1.
CP384 Configuration Table 4-19: Output Status Register BITS TYPE DEFAULT FUNCTION 31 r 0 Fail 30 r 0 Diag 29 - 0 r 0 Reserved BITS TYPE DEFAULT FUNCTION 31 r/w 0 Not used 30 r/w 0 Input compare interrupt enable 29 - 0 r/w 0 Input event interrupt enable 4.4.10 Programming the Board Capability ROM The Board Capability ROM contains all the board data necessary to identify board, version, optional features, etc., and to setup the basic software.
Configuration CP384 Table 4-22: ROM Control Register BITS TYPE DEFAULT FUNCTION 31-19 r/w 0 Reserved 17-16 r/w 00 Opcode 15-8 r/w 00 Reserved 8-0 r/w 00 Internal address (A8 ... A0) Note ... Table 4-23: Opcodes and Commands OPCODE A8 ... A0 COMMAND 00 11xxxxxxx EWEN 10 xxxxxxxxx READ 01 xxxxxxxxx WRITE Note ... The EWEN (Erase and Write Enable) command must be executed once before the first write.
System Considerations Chapter 51 RevNr. = CP384 - 31440_01 - 060503/144233 System Considerations ID 31440, Rev.
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CP384 System Considerations 5. System Considerations 5.1 Introduction In addition to the basic specification requirements for the CP384 which have been addressed in chapter 4, system integrators need to be aware of the overall system environment and the application needs when designing the interfacing to the CP384. The following chapters address a number of more apparent considerations which should be addressed, but certainly not all of the possible situations which may be encountered.
System Considerations CP384 CLOCK DIVIDER INPUT SAMPLE CLOCK @ 33 MHz PCI CLK INPUT SAMPLE PERIOD @ 33 MHz PCI CLK 1 (default value - see note below) 33 MHz 30 ns 2^8 128 kHz 8 µs 2^10 32 kHz 32 µs 2^12 8 kHz 128 µs 2^14 2 kHz 0.5 ms 2^16 0.5 kHz 2 ms 2^18 125 Hz 8 ms 2^20 31 Hz 32 ms Note ... The clock divider default value is 1. In addition to the choice of debouncing filters, there is an analog filter implemented on board with an edge frequency at 10 kHz. 5.