Instruction Manual

Configuration CP372

25780.01.VC.021121/111238

P R E L I M I N A R Y

4.3.2 DAC Control Logic

This part of the IO Control Logic controls the communication with the DAC. The DAC integrates

4 channels per chip (2 clusters for a total of 8 channels) and has a serial bus interface operating

at 2 MHz.

DAC operating mode is individually programmable for each channel, i.e. the polarity (unipolar/

bipolar) and range (5/10V and 20mA). After initialization of the corresponding DAC Control

Registers an Enable Bit must be set to ‘1’.

The DAC Control Logic handles the cyclic setup of the necessary DAC control word including

start bit, channel address, channel mode, and clock mode without any software intervention.

The digital output data are automatically stored in dual-ported data registers. An arbiter avoids

access conflicts between PCI access and DAC access to the same data register.

The architecture of the CP372 integrates the memory mapped data registers which are visible

to the programmer only and the actual DAC channel registers which are not visible to the pro-

grammer. Data is serialized and transferred between data register and the actual DAC by a

hardware sequencer automatically and continuously in a loop.

The DAC data registers can be written to at any time and independently of whether the DAC

cluster is enable or not.

+ 0x3000 4 kB DAC CLUSTER B

0x3400 32 bit ctl_b, Cluster b Common Control Register

0x3C00 32 bit dat_b_0 DAC Data channel # 0

0x3C04 32 bit dat_b_1 DAC Data channel # 1

0x3C08 32 bit dat_b_2 DAC Data channel # 2

0x3C0C 32 bit dat_b_3 DAC Data channel # 3

+0x4000

0xFFFF

48 kB reserved for additional clusters

Table 4-1: I/O Address Map of CP372

BASE

ADDRESS

(BAR0)

SIZE FUNCTION