User guide

Configuration CP371

4.3 Programming Interface

4.3.1 Access Control Logic

All the resources of the CP371 are mapped within the 64KB PCI memory address space which

itself is set in the PCI configuration register BAR0. The port size of all local or backend registers

is 32-bit by default. The address map of the registers is as follows.

Table 4-1: Backend Register Address Map

BASE

ADDRESS

(BAR0)

SIZE FUNCTION

+ 0x0000 4 kB COMMON BOARD REGISTER

0x0800 32 bit com_sta Hardware Status Register

0x0C00 32 bit com_ctl Hardware Debug Register

+ 0x1000 4 kB CAPABILITY ROM, SERIAL EEPROM

0x1000 32 bit cmd_r Command Register

0x1400 32 bit ctl_r Control Register

0x1800 32 bit sta_r Status Regsiter

0x1C00 32 bit dat_r Data Register

+ 0x2000 4 kB ADC CLUSTER A

0x2400 32 bit ctl_a, Cluster a Common Control Register

0x2C00 32 bit dat_a_0 ADC Data channel # 0

0x2C04 32 bit dat_a_1 ADC Data channel # 1

0x2C08 32 bit dat_a_2 ADC Data channel # 2

0x2C0C 32 bit dat_a_3 ADC Data channel # 3

0x2C10 32 bit dat_a_4 ADC Data channel # 4

0x2C14 32 bit dat_a_5 ADC Data channel # 5

0x2C18 32 bit dat_a_6 ADC Data channel # 6

0x2C1C 32 bit dat_a_7 ADC Data channel # 7