Manual

79 AT8050
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Dependent ClockId 6
Features 0x02
7:2 0h (reserved) [1] 1b = Connected through PLL [0] 0b =
Clock Receiver
Dependent ClockId 7
Direct clock Descriptor none
Clock Id 0x02 Receiver input from CLK2A
Clock Control 0x01 7:1 0h (reserved) [0] 1b = Activated by Application
Indirect Clock Descriptors Count(m) 0x02
Direct Clock Descriptors Count(n) 0x00
Indirect clock Descriptor
Features 0x02
7:2 0h (reserved) [1] 1b = Connected through PLL [0] 0b =
Clock Receiver
Dependent ClockId 6
Features 0x02
7:2 0h (reserved) [1] 1b = Connected through PLL [0] 0b =
Clock Receiver
Dependent ClockId 7
Direct clock Descriptor none
Clock Id 0x03 Receiver input from CLK2B
Clock Control 0x01 7:1 0h (reserved) [0] 1b = Activated by Application
Indirect Clock Descriptors Count(m) 0x02
Direct Clock Descriptors Count(n) 0x00
Indirect clock Descriptor
Features 0x02
7:2 0h (reserved) [1] 1b = Connected through PLL [0] 0b =
Clock Receiver
Dependent ClockId 6
Features
7:2 0h (reserved) [1] 1b = Connected through PLL [0] 0b =
Clock Receiver
Dependent ClockId 7
Direct clock Descriptor none
Clock Id 0x04 Source output to CLK3A
Clock Control 0x01 7:1 0h (reserved) [0] 1b = Activated by Application
Indirect Clock Descriptors Count(m) 0x02
Direct Clock Descriptors Count(n) 0x00
Indirect clock Descriptor
Features 0x01
7:2 0h (reserved) [1] 0b = Not Connected through PLL [0] 1b =
Clock Source
Dependent ClockId 8
Features 0x01
7:2 0h (reserved) [1] 0b = Not Connected through PLL [0] 1b =
Clock Source
Dependent ClockId 9
Direct clock Descriptor none
Clock Id 0x05 Source output to CLK3B
Clock Control 0x01 7:1 0h (reserved) [0] 1b = Activated by Application
Indirect Clock Descriptors Count(m) 0x02
Field Value Description