Specifications

Cinterion
®
PLS8-X/PLS8-V Hardware Interface Description
Figures
105
 PLS8-X_PLS8-V_HD_v03.016 2015-12-09
Confidential / Released
Page 7 of 105
Figures
Figure 1: PLS8-X/PLS8-V system overview.................................................................. 19
Figure 2: PLS8-X/PLS8-V block diagram...................................................................... 20
Figure 3: Decoupling capacitor(s) for BATT+................................................................ 23
Figure 4: Power supply limits during transmit burst....................................................... 24
Figure 5: Power-on with IGT ......................................................................................... 25
Figure 6: Signal states during turn-off procedure.......................................................... 27
Figure 7: Timing of IGT if used as ON/OFF switch ....................................................... 28
Figure 8: Shutdown by EMERG_OFF signal................................................................. 32
Figure 9: Wake-up via RTS0......................................................................................... 34
Figure 10: RTC supply variants....................................................................................... 35
Figure 11: USB circuit ..................................................................................................... 36
Figure 12: Serial interface ASC0..................................................................................... 38
Figure 13: First UICC/SIM/USIM interface ...................................................................... 41
Figure 14: Second UICC/SIM/USIM interface................................................................. 41
Figure 15: SIM interface - enhanced ESD protection...................................................... 42
Figure 16: PWR_IND signal ............................................................................................ 45
Figure 17: Low current indication timing (still to be confirmed) ....................................... 47
Figure 18: LED circuit (example)..................................................................................... 48
Figure 19: Antenna pads (bottom view) .......................................................................... 52
Figure 20: Embedded Stripline line arrangement............................................................ 53
Figure 21: Micro-Stripline line arrangement samples...................................................... 54
Figure 22: Routing to application‘s RF connector ........................................................... 55
Figure 23: PLS8-X/PLS8-V evaluation board layer table................................................ 55
Figure 24: Supply voltage for active GNSS antenna....................................................... 56
Figure 25: ESD protection for passive GNSS antenna ................................................... 57
Figure 26: Board and ambient temperature differences.................................................. 59
Figure 27: Bending test setup ......................................................................................... 62
Figure 28: PLS8-X/PLS8-V bottom view: Pad assignments............................................ 65
Figure 29: PLS8-X/PLS8-V top view: Pad assignments.................................................. 66
Figure 30: PLS8-X/PLS8-V – top and bottom view ......................................................... 82
Figure 31: Dimensions of PLS8-X/PLS8-V (all dimensions in mm)................................. 83
Figure 32: Land pattern (top layer).................................................................................. 84
Figure 33: Recommended design for 110 micron thick stencil (top layer) ...................... 85
Figure 34: Recommended design for 150 micron thick stencil (top layer) ...................... 85
Figure 35: Reflow Profile................................................................................................. 87
Figure 36: Carrier tape .................................................................................................... 90
Figure 37: Roll direction .................................................................................................. 90
Figure 38: Barcode label on tape reel............................................................................. 91
Figure 39: Moisture barrier bag (MBB) with imprint......................................................... 92
Figure 40: Moisture Sensitivity Label .............................................................................. 93
Figure 41: Humidity Indicator Card - HIC ........................................................................ 94
Figure 42: PLS8-X/PLS8-V sample application............................................................... 96
Figure 43: Sample level conversion circuit...................................................................... 97
Figure 44: Reference equipment for type approval......................................................... 98