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Memory Module Specifications

VALUERAM0889-001.A00 02/02/10 Page 1

This document describes ValueRAM’s 512M x 72-bit (4GB) PC2-5300 CL5 SDRAM (Synchronous DRAM) fully

buffered ECC quad rank memory module. This module is based on thirty-six 128M x 8-bit 667MHz DDR2 FBGA

components. The module also includes an AMB device (Advanced Memory Buffer). The electrical and mechanical

specifications are as follows:

Description:

KVR667D2Q8F5/4GHE

4GB 512M x 72-Bit PC2-5300

CL5 ECC 240-Pin FBDIMM

· FBDIMM Module: 240-pin

· JEDEC Standard

· Memory Organization: 4 rank of x8 devices

· DDR2 DRAM Interface: SSTL_18

· DDR2 Speed Grade: 667 Mbps

· CAS Latency: 5-5-5

· Module Bandwidth: 5.3 GB/s

· DRAM: VDD = VDDQ = 1.8V

· AMB: VCC = VCCFBD = 1.5V

· EEPROM: VDDSPD = 3.3V (typical)

· Heat Spreader: Full DIMM Heat Spreader (FDHS)

· PCB Height: 30.35mm, double-side

· RoHS Compliant

Feature:

DRAM Supported:

Hynix E-die

Summary of content (7 pages)

PAGE 1
Memory Module Specifications KVR667D2Q8F5/4GHE 4GB 512M x 72-Bit PC2-5300 CL5 ECC 240-Pin FBDIMM Description: This document describes ValueRAM’s 512M x 72-bit (4GB) PC2-5300 CL5 SDRAM (Synchronous DRAM) fully buffered ECC quad rank memory module. This module is based on thirty-six 128M x 8-bit 667MHz DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer).
PAGE 2
T E C H N O L O G Y DDR2 240-pin FBDIMM Pinout: Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side 1 VDD 121 VDD 31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 SS9 2 VDD 122 VDD 32 PN3 152 SN3 62 VSS 182 VSS 92 VSS 212 VSS 3 VDD 123 VDD 33 VSS 153 VSS 63 PN10 183 SN10 93 PS5 213 SS5 4 VSS 124 VSS 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5 5 VDD 125
PAGE 3
T E C H N O L O G Y DIMM Connector Pin Description: Pin Name Pin Description Count SCK System Clock Input, positive line1 1 SCK System Clock Input, negative line1 1 PN[13:0] Primary Northbound Data, positive lines 14 PN[13:0] Primary Northbound Data, negative lines 14 PS[9:0] Primary Southbound Data, positive lines 10 Primary Southbound Data, negative lines 10 SN[13:0] Secondary Northbound Data, positive lines 14 SN[13:0] Secondary Northbound Data, negative lines 14 SS[9:0] Secon
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T E C H N O L O G Y Functional Block Diagram: S3 S2 S1 S0 DQS0 DQS0 DQS9 DQS4 DQS4 DQS13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS D0 D9 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ NU/ CS DQS DQS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D18 DM/ NU/ CS DQS DQS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D27 DQS1 DQS1 DQ
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T E C H N O L O G Y Architecture: Advanced Memory Buffer Pin Description: Pin Name Pin Description Count FB-DIMM Channel Signals 99 SCK System Clock Input, positive line 1 SCK System Clock Input, negative line 1 PN[13:0] Primary Northbound Data, positive lines 14 PN[13:0] Primary Northbound Data, negative lines 14 PS[9:0] Primary Southbound Data, positive lines 10 PS[9:0] Primary Southbound Data, negative lines 10 SN[13:0] Secondary Northbound Data, positive lines 14 SN[13:0] Sec
PAGE 6
T E C H N O L O G Y Advanced Memory Buffer Pin Description: SPD Bus Interface Signals 5 SCL Serial Presence Detect (SPD) Clock Input 1 SDA SPD Data Input / Output 1 SPD Address Inputs, also used to select the DIMM number in the AMB 3 SA[2:0] Miscellaneous Signals 163 PLLTSTO PLL Clock Observability Output 1 VCCAPLL Analog VCC for the PLL. Tied with low pass filter to VCC. 1 VSSAPLL Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.
PAGE 7
T E C H N O L O G Y Package Dimensions: VALUERAM0889-001.