User Manual

VS1003
10 VS1003 REGISTERS
10.6 DAC Registers
DAC registers, prefix DAC_
Reg Type Reset Abbrev[bits] Description
0xC013 rw 0 FCTLL DAC frequency control, 16 LSbs.
0xC014 rw 0 FCTLH DAC frequency control 4MSbs, PLL control.
0xC015 rw 0 LEFT DAC left channel PCM value.
0xC016 rw 0 RIGHT DAC right channel PCM value.
Every fourth clock cycle, an internal 26-bit counter is added to by (DAC_FCTLH & 15) × 65536
+ DAC_FCTLL. Whenever this counter overflows, values from DAC_LEFT and DAC_RIGHT
are read and a DAC interrupt is generated.
10.7 GPIO Registers
GPIO registers, prefix GPIO_
Reg Type Reset Abbrev[bits] Description
0xC017 rw 0 DDR[3:0] Direction.
0xC018 r 0 IDATA[3:0] Values read from the pins.
0xC019 rw 0 ODATA[3:0] Values set to the pins.
GPIO_DIR is used to set the direction of the GPIO pins. 1 means output. GPIO_ODATA
remembers its values even if a GPIO_DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note that in VS1003 the VSDSP registers can be read and written through the SCI_WRAMADDR
and SCI_WRAM registers. You can thus use the GPIO pins quite conveniently.
Version: 1.08, 2014-12-19 47