User Manual

VS1003

8 FUNCTIONAL DESCRIPTION

8.6.4 SCI_CLOCKF (RW)

The operation of SCI_CLOCKF is different in VS1003 than in VS1001, VS1011, and VS1002.

SCI_CLOCKF bits

Name Bits Description

SC_MULT 15:13 Clock multiplier

SC_ADD 12:11 Allowed multiplier addition

SC_FREQ 10: 0 Clock frequency

SC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.

The values are as follows:

SC_MULT MASK CLKI

0 0x0000 XTALI

1 0x2000 XTALI×1.5

2 0x4000 XTALI×2.0

3 0x6000 XTALI×2.5

4 0x8000 XTALI×3.0

5 0xa000 XTALI×3.5

6 0xc000 XTALI×4.0

7 0xe000 XTALI×4.5

SC_ADD tells, how much the decoder ﬁrmware is allowed to add to the multiplier speciﬁed by

SC_MULT if more cycles are temporarily needed to decode a WMA stream. The values are:

SC_ADD MASK Multiplier addition

0 0x0000 No modiﬁcation is allowed

1 0x0800 0.5×

2 0x1000 1.0×

3 0x1800 1.5×

SC_FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz.

XTALI is set in 4 kHz steps. The formula for calculating the correct value for this register is

XT ALI−8000000

4000

(XTALI is in Hz).

Note: The default value 0 is assumed to mean XTALI=12.288 MHz.

Note: because maximum sample rate is

XT ALI

256

, all sample rates are not available if XTALI

< 12.288 MHz.

Note: Automatic clock change can only happen when decoding WMA ﬁles. Automatic clock

change is done one 0.5× at a time. This does not cause a drop to 1.0× clock and you can

use the same SCI and SDI clock throughout the WMA ﬁle. When decoding ends the default

multiplier is restored and can cause 1.0× clock to be used momentarily.

Example: If SCI_CLOCKF is 0x9BE8, SC_MULT = 4, SC_ADD = 3 and SC_FREQ = 0x3E8 = 1000.

This means that XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to

3.0×XTALI = 36 MHz, and the maximum allowed multiplier that the ﬁrmware may automatically

choose to use is (3.0 + 1.5)×XTALI = 54 MHz.

Version: 1.08, 2014-12-19 32