User Manual
VS1003
8 FUNCTIONAL DESCRIPTION
8.5 Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are
always 16 bits. VS1003 is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
• control of the operation mode, clock, and builtin effects
• access to status information and header data
• access to encoded digital data
• uploading user programs
8.6 SCI Registers
SCI registers, prefix SCI_
Reg Type Reset Time
1
Abbrev[bits] Description
0x0 rw 0x800 70 CLKI
4
MODE Mode control
0x1 rw 0x3C
3
40 CLKI STATUS Status of VS1003
0x2 rw 0 2100 CLKI BASS Built-in bass/treble enhancer
0x3 rw 0 11000 XTALI
5
CLOCKF Clock freq + multiplier
0x4 rw 0 40 CLKI DECODE_TIME Decode time in seconds
0x5 rw 0 3200 CLKI AUDATA Misc. audio data
0x6 rw 0 80 CLKI WRAM RAM write/read
0x7 rw 0 80 CLKI WRAMADDR Base address for RAM
write/read
0x8 r 0 - HDAT0 Stream header data 0
0x9 r 0 - HDAT1 Stream header data 1
0xA rw 0 3200 CLKI
2
AIADDR Start address of application
0xB rw 0 2100 CLKI VOL Volume control
0xC rw 0 50 CLKI
2
AICTRL0 Application control register 0
0xD rw 0 50 CLKI
2
AICTRL1 Application control register 1
0xE rw 0 50 CLKI
2
AICTRL2 Application control register 2
0xF rw 0 50 CLKI
2
AICTRL3 Application control register 3
1
This is the worst-case time that DREQ stays low after writing to this register. The user may
choose to skip the DREQ check for those register writes that take less than 100 clock cycles to
execute.
2
In addition, the cycles spent in the user application routine must be counted.
3
Firmware changes the value of this register immediately to 0x38, and in less than 100 ms to
0x30.
4
When mode register write specifies a software reset the worst-case time is 16600 XTALI
cycles.
5
Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not
a good idea to send SCI or SDI bits while this register update is in progress.
Note that if DREQ is low when an SCI write is done, DREQ also stays low after SCI write
processing.
Version: 1.08, 2014-12-19 28