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nRF24L01+ Product Specification

Table 26. SPI timing parameters (R

pull

= 50k

, C

load

= 50pF)

Table 27. SPI timing parameters (R

pull

= 50k

, C

load

= 100pF)

8.4 Data FIFO

The data FIFOs store transmitted payloads (TX FIFO) or received payloads that are ready to be clocked

out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode.

The following FIFOs are present in nRF24L01+:

• TX three level, 32 byte FIFO

• RX three level, 32 byte FIFO

Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX

FIFO in PRX can store payloads for ACK packets to three different PTX devices. If the TX FIFO contains

more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX FIFO in

a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this

case, the MCU can flush the TX FIFO using the

FLUSH_TX command.

The RX FIFO in PRX can contain payloads from up to three different PTX devices and a TX FIFO in PTX

can have up to three payloads stored.

Symbol Parameters Min. Max Units

Tdc Data to SCK Setup 2 ns

Tdh

SCK to Data Hold 2 ns

Tcsd

CSN to Data Valid 75 ns

Tcd

SCK to Data Valid 85 ns

Tcl

SCK Low Time 40 ns

Tch

SCK High Time 40 ns

Fsck

SCK Frequency 0 5 MHz

Tr,Tf

SCK Rise and Fall 100 ns

Tcc

CSN to SCK Setup 2 ns

Tcch

SCK to CSN Hold 2 ns

Tcw h

CSN Inactive time 50 ns

Tcdz

CSN to Output High Z 75 ns