User Manual

Revision 1.0 Page 30 of 78
nRF24L01+ Product Specification
With the DPL feature the nRF24L01+ can decode the payload length of the received packet automatically
instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using
the R_RX_PL_WID command.
Note: Always check if the packet width reported is 32 bytes or shorter when using the
R_RX_PL_WID command. If its width is longer than 32 bytes then the packet contains errors
and must be discarded. Discard the packet by using the Flush_RX command.
In order to enable DPL the EN_DPL bit in the FEATURE register must be enabled. In RX mode the DYNPD
register must be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD
set.
7.3.5 CRC (Cyclic Redundancy Check)
The CRC is the mandatory error detection mechanism in the packet. It is either 1 or 2 bytes and is calcu-
lated over the address, Packet Control Field and Payload.
The polynomial for 1 byte CRC is X
8
+ X
2
+ X + 1. Initial value 0xFF.
The polynomial for 2 byte CRC is X
16
+ X
12
+ X
5
+ 1. Initial value 0xFFFF.
The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. No packet is accepted by
Enhanced ShockBurst™ if the CRC fails.