User manual

Chapter 4 Remote Interface Reference
The SCPI Status Registers
94
The Standard Event register is cleared when:
*CLS
*ESR?
The Standard Event Enable register is cleared when:
*ESE 0
*PSC 1
*PSC 0
The Status Byte Register
Table 4-5. Bit Definitions – Status Byte Summary Register
Bit Decimal
Value
Definition
0-2 Not Used 0 Always set to 0.
3 QUES
8
One or more bits are set in the questionable status
register (bits must be “enabled” in the enable register).
4 MAV 16 Data is available in the power supply output buffer.
5 ESB
32
One or more bits are set in the standard event register
(bits must be “enabled” in the enable register).
6 RQS 64 The power supply is requesting service (serial poll).
7 Not Used 0 Always set to 0.