User manual

3390-900-01 Rev. C / January 2009 Return to Section Topics A-7
Model 3390 Arbitrary Waveform Generator User’s Manual Appendix A: SCPI Command Reference
Status register sets
Condition register: Contains the current status of the hardware and firmware, is continuously
updated, and is not latched or buffered. Condition registers are read-only.
Event register: Latches transition events from the condition register. Event registers are cleared
by reading, by query command, or with the *CLS command. Event registers are read-only, and bits
are not buffered, so subsequent events are not recorded.
Enable register: Defines which bits in an event register are included in the Logic OR, and entered
into the summary bit. These bits are then reported to the Status Byte Register. Enable registers are
read-write and are not affected by *CLS or querying.
Status Byte Register and service request
The Status Byte Register summarizes the information from all other status groups. The summary
bit for the Status Byte Register is located in Bit 6, request for service (RQS). When RQS is set, it
generates a service request (SRQ) on the IEEE-488 bus.
The Status Byte Register is read using a serial poll sequence or with the *STB? query. An SRQ is
enabled by setting the associated bit in the Service Request Enable Register with the *SRE
command. This register can be read using the *SRE? query.
Clear the Status Byte condition register by reading an event register from another group, or with a
*CLS (clear status) command. Clear the Status Byte enable register with an *SRE 0 command.
You can also set the instrument to clear the enable register using the *PSC 1 command; the
instrument will clear the enable register at power up.
Bits in the Status Byte Register are summarized in Table A-3.
Table A-3:
Status Byte register
Bit Decimal value Description
0 1 Not used (always 0).
1 2 Not used (always 0).
2 4 Error queue stores one or more errors.
3 8 Questionable Data Register contains one or more bits.
4 16 Output buffer contains available message (data).
5 32 Standard Event Register contains one or more bits.
6 64 Status Byte Register contains one or more bits.
7 128 Not used (always 0).